Nonideal

Transistor
Theory
1
 Outline
 Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
 Process and Environmental Variations

CMOS VLSI Design 4th Ed. 2

 Ideal Transistor I-V
 Shockley long-channel transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds     Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 4th Ed. 3

Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V
Ids (A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1

CMOS VLSI Design 4th Ed. 4

 ON and OFF Current
Ids (A)

 Ion = Ids @ Vgs = Vds = VDD 1000

Ion = 747 mA @
Vgs = Vds = VDD

800 Vgs = 1.0

– Saturation 600

Vgs = 0.8

400

Vgs = 0.6
200

Vgs = 0.4

0 Vds
0 0.2 0.4 0.6 0.8 1

 Ioff = Ids @ Vgs = 0, Vds = VDD

– Cutoff

CMOS VLSI Design 4th Ed. 5

 Electric Fields Effects
 Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel  Evert
 Lateral electric field: Elat = Vds / L
– Accelerates carriers from drain to source
– Long channel: v = Elat

CMOS VLSI Design 4th Ed. 6

 Coffee Cart Analogy
 Tired student runs from VLSI lab to coffee cart
 Freshmen are pouring out of the physics lecture hall
 Vds is how long you have been up
– Your velocity = fatigue × mobility
 Vgs is a wind blowing you against the glass (SiO2) wall
 At high Vgs, you are buffeted against the wall
– Mobility degradation
 At high Vds, you scatter off freshmen, fall down, get up
– Velocity saturation
• Don’t confuse this with the saturation region
CMOS VLSI Design 4th Ed. 7
 Mobility Degradation
 High Evert effectively reduces mobility
– Collisions with oxide interface

CMOS VLSI Design 4th Ed. 8

 Velocity Saturation
 At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Better model

CMOS VLSI Design 4th Ed. 9

 Vel Sat I-V Effects
 Ideal transistor ON current increases with VDD2
W Vgs  Vt 
2

 Vgs  Vt 
2
I ds  Cox
L 2 2

 Velocity-saturated ON current increases with VDD

I ds  CoxW Vgs  Vt  vmax

 Real transistors are partially velocity saturated

– Approximate with -power law model
– Ids  VDD
– 1 <  < 2 determined empirically (≈ 1.3 for 65 nm)
CMOS VLSI Design 4th Ed. 10
 -Power Model
 0 Vgs  Vt cutoff 
 Pc Vgs  Vt 

 I dsat
 V
I ds   I dsat ds Vds  Vdsat linear 2
 Vdsat
Vdsat  Pv Vgs  Vt 
 /2
 I dsat Vds  Vdsat saturation

CMOS VLSI Design 4th Ed. 11

Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
GND VDD VDD

– Leff = L – Ld Source Gate Drain

Depletion Region
Width: Ld
 Shorter Leff gives more current
– Ids increases with Vds n
+
L n
+
Leff

– Even in saturation p GND bulk Si

CMOS VLSI Design 4th Ed. 12

 Chan Length Mod I-V


I ds  Vgs  Vt  1  Vds 
2

  = channel length modulation coefficient

– not feature size
– Empirically fit to I-V characteristics

CMOS VLSI Design 4th Ed. 13

 Threshold Voltage Effects
 Vt is Vgs for which the channel starts to invert
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect

CMOS VLSI Design 4th Ed. 14

 Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0    s  Vsb  s 
 s = surface potential at threshold
NA
s  2vT ln
ni

– Depends on doping level NA

– And intrinsic carrier concentration ni
  = body effect coefficient
tox 2q si N A
  2q si N A 
 ox Cox

CMOS VLSI Design 4th Ed. 15

 Body Effect Cont.
 For small source-to-body voltage, treat as linear

CMOS VLSI Design 4th Ed. 16

 DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
VVV
ttds

– Drain voltage also affect Vt

Vt   Vt  Vds
 High drain voltage causes current to increase.

CMOS VLSI Design 4th Ed. 17

 Short Channel Effect
 In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes Vt a function of channel length
 Short channel effect: Vt increases with L
– Some processes exhibit a reverse short channel
effect in which Vt decreases with L

CMOS VLSI Design 4th Ed. 18

 Leakage
 What about current in cutoff?
 Simulated results
 What differs?
– Current doesn’t
go to 0 in cutoff

CMOS VLSI Design 4th Ed. 19

 Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current

CMOS VLSI Design 4th Ed. 20

 Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
Vgs Vt 0 Vds  k Vsb Vds
nvT
 
I ds  I ds 0 e 1  e vT 
 
 
 n is process dependent
– typically 1.3-1.7
 Rewrite relative to Ioff on log scale

 S ≈ 100 mV/decade @ room temperature

CMOS VLSI Design 4th Ed. 21

 Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD

– A and B are tech constants

– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (tox > 20 Å)
From [Song01]

 Critically important at 65 nm and below (tox ≈ 10.5 Å)

CMOS VLSI Design 4th Ed. 22
 Junction Leakage
 Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)

p+ n+ n+ p+ p+ n+
n well
p substrate

CMOS VLSI Design 4th Ed. 23

 Diode Leakage
 Reverse-biased p-n junctions have some leakage
 VvD 
I D  I S  e  1
T

 
 
 At any significant negative diode voltage, ID = -Is
 Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/m2 (negligible)

CMOS VLSI Design 4th Ed. 24

 Band-to-Band Tunneling
 Tunneling across heavily doped p-n junctions
– Especially sidewall between drain & channel
when halo doping is used to increase Vt
 Increases junction leakage to significant levels

– Xj: sidewall junction depth

– Eg: bandgap voltage
– A, B: tech constants
CMOS VLSI Design 4th Ed. 25
Gate-Induced Drain Leakage
 Occurs at overlap between gate and drain
– Most pronounced when drain is at VDD, gate is at
a negative voltage
– Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

CMOS VLSI Design 4th Ed. 26

Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature

I ds

increasing
temperature

Vgs

CMOS VLSI Design 4th Ed. 27

 So What?
 So what if transistors are not ideal?
– They still behave like switches.
 But these effects matter for…
– Supply voltage choice
– Logical effort
– Quiescent power consumption
– Pass transistors
– Temperature of operation

CMOS VLSI Design 4th Ed. 28

 Parameter Variation
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
 Fast (F)

fast
FF
SF

– Leff: short

pMOS
TT

– Vt: low
FS

– tox: thin SS

slow
 Slow (S): opposite slow
nMOS
fast

 Not all parameters are independent

for nMOS and pMOS
CMOS VLSI Design 4th Ed. 29
Environmental Variation
 VDD and T also vary in time and space
 Fast:
– VDD: high
– T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C

CMOS VLSI Design 4th Ed. 30

 Process Corners
 Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature

CMOS VLSI Design 4th Ed. 31

 Important Corners
 Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold F F F S
leakage

CMOS VLSI Design 4th Ed. 32