Introduction to CMOS VLSI Design

Chapter 5
Power

Slide 1
CMOS VLSI Design
 Outline
 Power and Energy
 Dynamic Power
 Static Power

Chapter 5 CMOS VLSI Design 2

 Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

 Instantaneous Power: P (t )  I (t )V (t )
T
 Energy: E   P (t )dt
0
T
 Average Power: E 1
Pavg    P (t )dt
T T 0

Chapter 5 CMOS VLSI Design 3

 Power versus Energy
Power is height of curve
Watts Lower power design could simply be slower
Approach 1

Approach 2

time
Energy is area under curve
Watts Two approaches require the same energy
Approach 1

Approach 2

time
Chapter 5 CMOS VLSI Design Slide 4
Power Dissipation Sources
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit (crowbar) current
 Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current

Chapter 5 CMOS VLSI Design 5

 Power in Circuit Elements
PVDD t   I DD t VDD

VR2 t 
PR t    I R2 t  R
R

 
dV
EC   I t V t  dt   C V t  dt
0 0
dt
VC

 C  V t dV  12 CVC2
0

Chapter 5 CMOS VLSI Design 6

 Charging a Capacitor
 When the gate output rises
– Energy stored in capacitor is
2
EC  12 CLVDD
– But energy drawn from the supply is
 
dV
EVDD   I t VDD dt   CL VDD dt
0 0
dt
VDD

 dV  C V
2
 CLVDD L DD
0

– Half the energy from VDD is dissipated in the pMOS

transistor as heat, other half stored in capacitor
 When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor
Chapter 5 CMOS VLSI Design 7
 Switching Waveforms
 Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

Chapter 5 CMOS VLSI Design 8

 Switching Power
T
1
Pswitching   iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt

VDD
 Tfsw CVDD  VDD
T iDD(t)
fsw

 CVDD 2 f sw
C

Chapter 5 CMOS VLSI Design 9

 Dynamic Power
Vdd

Vin Vout

CL
f01
Energy/transition = CL * VDD * P01
2

Pdyn = Energy/transition * f = CL * VDD2 * P01 * f

Data dependent - a function of switching activity!

Chapter 5 CMOS VLSI Design Slide 10

 Activity Factor
 Suppose the system clock frequency = f
 Let fsw = af, where a = activity factor
– If the signal is a clock, a = 1
– If the signal switches once per cycle, a = ½

 Dynamic power:
Pswitching   CVDD 2 f

Chapter 5 CMOS VLSI Design 11

Reducing Dynamic Power
Capacitance: Supply Voltage:
Function of fan-out, Has been dropping
wire length, transistor with successive
sizes generations

Pdyn = CL VDD2 P01 f

Activity factor: Clock frequency:

How often, on average, Increasing…
do wires switch?

Chapter 5 CMOS VLSI Design Slide 12

 Low V-Swing Signaling
 Driver power
 Receiver power
 Latching receivers

Chapter 5 CMOS VLSI Design Slide 13

 Short Circuit (Crowbar)
Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output
 We will generally ignore this component.
It is included in circuit simulation

Chapter 5 CMOS VLSI Design 14

 Short Circuit Power

Vin Isc Vout

CL

Finite slope of the input signal causes a direct

current path between VDD and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Chapter 5 CMOS VLSI Design Slide 15
 Short Circuit Currents
Esc = tsc VDD Ipeak P01

Psc = tsc VDD Ipeak f01

 Duration and slope of the input signal, tsc
 Ipeak determined by
– the saturation current of the P and N transistors which
depend on their sizes, process technology, temperature, etc.
– strong function of the ratio between input and output slopes
• a function of CL

Chapter 5 CMOS VLSI Design Slide 16

 Impact of CL on Psc
in next Stage
Isc  0 Isc  Imax
Vin Vout Vin Vout

CL CL

Large capacitive load Small capacitive load

Output fall time significantly Output fall time substantially

larger than input rise time. smaller than the input rise
time.
Chapter 5 CMOS VLSI Design Slide 17
Dynamic Power Example
 1 billion transistor chip
– 50M logic transistors
• Average width: 12 l
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 l
• Activity factor = 0.02
– 1.0 V 50 nm process
– C = 1 fF/mm (gate) + 0.8 fF/mm (diffusion)
 Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

Chapter 5 CMOS VLSI Design 18

 Solution
Clogic  50 106  12  0.025 m /  1.8 fF /  m   27 nF
Cmem  950 106   4  0.025 m /  1.8 fF /  m   171 nF

Pdynamic  0.1Clogic  0.02Cmem  1.0  1.0 GHz   6.1 W

2

Chapter 5 CMOS VLSI Design 19

 Dynamic Power Reduction
2
P
 switching   CVDD f

 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Voltage swing
– Frequency

Chapter 5 CMOS VLSI Design 20

 Activity Factor Estimation
 Let Pi = Prob(node i = 1)
– Pi = 1-Pi
 ai = Pi * Pi
 Completely random data has P = 0.5 and a = 0.25
 Data is often not completely random
– e.g. upper bits of 64-bit words representing bank
account balances are usually 0
 Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically a ≈ 0.1

Chapter 5 CMOS VLSI Design 21

 Gates and Probability

Chapter 5 CMOS VLSI Design 22

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5 and inputs are uncorrelated with each
other and in time:

Chapter 5 CMOS VLSI Design 23

 Transition Probabilities
 Switching activity is a strong function of the input signal statistics
– PA and PB are the probabilities that inputs A and B are one

0
A B CL
PA
1 0 1
PB
P01 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

Chapter 5 CMOS VLSI Design Slide 24

 Transition Probabilities
P01 = Pout=0 x Pout=1
NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)
OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))
NAND PAPB x (1 - PAPB)
AND (1 - PAPB) x PAPB
XOR (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)

X
0.5 A
Z
0.5 B
For X: P01 = P0 x P1 = (1-PA) PA = 0.5 x 0.5 = 0.25

For Z: P01 = P0 x P1 = (1-PXPB) PXPB = (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16

Chapter 5 CMOS VLSI Design Slide 25

 Inter-signal Correlations
 Determining switching activity is complicated by the fact
that signals exhibit correlation in space and time
– reconvergent fan-out
(1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16
0.5 A
X
0.5 B
Z

(1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085

Reconvergent
is P(Z=1) = P(B=1) & P(A=1 | B=1) ? What is Z?
 Have to use conditional probabilities
Chapter 5 CMOS VLSI Design Slide 26
 Logic Restructuring
 Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P01 = P0 x P1 = (1 - PAPB) x PAPB
3/16
0.5 A Y
0.5 (1-0.25)*0.25 = 3/16
A W 7/64 0.5 B 15/256
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16

Chain implementation has a lower overall switching activity

than the tree implementation for random inputs
Ignores glitching effects

Chapter 5 CMOS VLSI Design Slide 27

 Input Ordering

(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5

Beneficial to postpone the introduction of signals with a high

transition rate (signals with signal probability close to 0.5)

Chapter 5 CMOS VLSI Design Slide 28

 Glitching
 Gates have a nonzero propagation delay resulting in spurious transitions or
glitches (dynamic hazards)
– glitch: node exhibits multiple transitions in a single cycle before settling
to the correct logic value A X
B
C Z

ABC 101 000

Unit Delay
Chapter 5 CMOS VLSI Design Slide 29
 Balanced Delay Paths
 Glitching is due to a mismatch in the path lengths in
the logic network; if all input signals of a gate change
simultaneously, no glitching occurs
0 0
0 F1 1 0 F1 1
0 F2 2
F3
0 F3 0
0 F2 1

So equalize the lengths of timing paths through logic

Chapter 5 CMOS VLSI Design Slide 30

 Clock Gating
 The best way to reduce the activity is to turn off the
clock to registers in unused blocks
– Saves clock activity (a = 1)
– Eliminates all switching activity in the block
– Requires determining if block will be used

Chapter 5 CMOS VLSI Design 31

 Capacitance
 Gate capacitance
– Fewer stages of logic
– Small gate sizes
 Wire capacitance
– Good floorplanning to keep communicating
blocks close to each other
– Drive long wires with inverters or buffers rather
than complex gates

Chapter 5 CMOS VLSI Design 32

 Voltage / Frequency
 Run each block at the lowest possible voltage and
frequency that meets performance requirements
 Voltage Domains
– Provide separate supplies to different blocks
– Level converters required when crossing
from low to high VDD domains

 Dynamic Voltage Scaling

– Adjust VDD and f according to
workload

Chapter 5 CMOS VLSI Design 33

 Multiple VDD Domains
 IO / core
– 2.5V or 3.3V IO to interface with chips using
existing standards
– 1.2V to 0.8V core for small geometry transistors
– Need 2 thicknesses of gate oxides
 Still lower power, low speed circuits in the core
 How to get signals between VDD domains?

 Multiple core supplies not as popular as multiple VT masks

– High VT for low power (low leakage, low crowbar)
– Low VT for high speed (high current)
Chapter 5 CMOS VLSI Design Slide 34
 Multiple VDD
 How many VDD? – Two is becoming common
– Many chips already have two supplies (one for core and one for I/O)
 When combining multiple supplies, level converters are required whenever a
module at the lower supply drives a gate at the higher supply (step-up)
– If a gate supplied with VDDL drives a gate at VDDH, the PMOS never turns
off
• The cross-coupled PMOS transistors VDDH do the level
conversion
• The NMOS transistor operate on a
Vout
reduced supply VDDL
– Level converters are not needed Vin for a
step-down change in voltage
– Overhead of level converters can be mitigated by doing conversions at
register boundaries and embedding the level conversion inside the flipflop

Chapter 5 CMOS VLSI Design Slide 35

 Dual-Supplies
 Minimum energy consumption is achieved if all logic paths are critical
(have the same delay)
 Clustered voltage-scaling
– Each path starts with VDDH and switches to VDDL (gray logic gates)
when delay slack is available
– Level conversion is done in the flipflops at the end of the paths

VDDL

Chapter 5 CMOS VLSI Design Slide 36

 Static Power
 Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices
– Ratioed circuits burn power in fight between ON
transistors

Chapter 5 CMOS VLSI Design 37

 Leakage Power
VDD Ileakage
Vout
Drain junction
leakage

Gate leakage Sub-threshold current

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

Chapter 5 CMOS VLSI Design Slide 38
 Leakage and VT
 Continued scaling of supply voltage and the subsequent
scaling of threshold voltage will make subthreshold
conduction a dominant component of power dissipation.
10-2
 Each 255mV
increase in VT gives
3 orders of
10-7
magnitude reduction
in leakage (but
ID (A)

adversely affects
VT=0.4V
VT=0.1V
performance)

10-12 0 0.2 0.4 0.6 0.8 1

VGS (V)

Chapter 5 CMOS VLSI Design Slide 39

Leakage Current Increase
10000

1000
Ileakage(nA/m)

0.25
0.18
100
0.13
0.1

10

1
30 40 50 60 70 80 90 100 110
Temp(C)

Chapter 5 CMOS VLSI Design From De,1999

Slide 40
 Static Power Example
 Revisit power estimation for 1 billion transistor chip
 Estimate static power consumption
– Subthreshold leakage
• Normal Vt: 100 nA/mm
• High Vt: 10 nA/mm
• High Vt used in all memories and in 95% of
logic gates
– Gate leakage 5 nA/mm
– Junction leakagenegligible

Chapter 5 CMOS VLSI Design 41

 Solution
Wnormal-Vt  50 106  12  0.025 m /   0.05   0.75  106  m

Whigh-Vt  50 106  12  0.95   950  106   4   0.025 m /    109.25 10 6  m

I sub  Wnormal-Vt 100 nA/ m+Whigh-Vt  10 nA/ m  / 2  584 mA

 
I gate   Wnormal-Vt  Whigh-Vt  5 nA/ m  / 2  275 mA
 
Pstatic  584 mA  275 mA 1.0 V   859 mW

14% of 6.1W dynamic power

What if 90% idle?

Chapter 5 CMOS VLSI Design 42

 Subthreshold Leakage
 For Vds > 50 mV Typical values in 65 nm
Vgs  Vds VDD  k Vsb Ioff = 100 nA/mm @ Vt = 0.3 V
I sub  I off 10 S
Ioff = 10 nA/mm @ Vt = 0.4 V
Ioff = 1 nA/mm @ Vt = 0.5 V
 Ioff = leakage at Vgs = 0, Vds = VDD h = 0.1
kg = 0.1
S = 100 mV/decade

Chapter 5 CMOS VLSI Design 43

 Stack Effect
 Series OFF transistors have less leakage
– Vx > 0, so N2 has negative Vgs
 Vx VDD  Vx  VDD Vx VDD  k Vx

I sub  I off 10  I off 10

S S
              
N2 N1

VDD
Vx 
1  2  k
 1  k 
VDD  
 1 2  k  VDD
 
I sub  I off 10 S
 I off 10 S

Chapter 5 CMOS VLSI Design 44

 Leakage Control
 Leakage and delay trade off
– Aim for low leakage in sleep and low delay in
active mode
 To reduce leakage:
– Increase Vt: multiple Vt
• Use low Vt only in critical circuits
– Increase Vs: stack effect
• Input vector control in sleep
– Decrease Vb
• Reverse body bias in sleep
• Or forward body bias in active mode

Chapter 5 CMOS VLSI Design 45

 Gate Leakage
 Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and
below in some processes
 An order of magnitude less for pMOS than nMOS
 Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
 Control leakage in circuits by limiting VDD

Chapter 5 CMOS VLSI Design 46

 NAND3 Leakage Example
 100 nm process
Ign = 6.3 nA Igp = 0
Ioffn = 5.63 nA Ioffp = 9.3 nA

Data from [Lee03]

Chapter 5 CMOS VLSI Design 47

 Junction Leakage
 From reverse-biased p-n junctions
– Between diffusion and substrate or well
 Ordinary diode leakage is negligible
 Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other
leakage is small
– Worst at Vdb = VDD
 Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)

Chapter 5 CMOS VLSI Design 48

 Power Gating
 Turn OFF power to blocks when they are idle to
save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block

 Voltage drop across sleep transistor degrades

performance during normal operation
– Size the transistor wide enough to minimize
impact
 Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
Chapter 5 CMOS VLSI Design 49