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Week 04 Digital Design - 03 Gate Level Minimization 31032020 112339am
Week 04 Digital Design - 03 Gate Level Minimization 31032020 112339am
1
Grouping and Minimizing
Number of elements in a Groups must be 2n
where n=whole number
All 1s must be part of at least one group
Group size must be maximized: e.g. if a group can be formed of four, do
NOT make two groups (two in each).
1s can be shared among different groups
Minimizing
For each group, select only those variables that are NOT changing their value
throughout the group
Unchanged variables be named as x’ or x representing 0 or 1 in that group
2
Four Variable Maps
F(A,B,C,D) = Σ(0,1,2,4,5,6,8,9,12,13,14)
CD
AB 00 01 11 10
00 1 1 1
01 1 1 1
11 1 1 1
10 1 1
F = C’ + A’D’ + BD’
3
Four Variable Maps
F(A,B,C,D) = Σ(0,1,4,5,10,11)
CD
AB 00 01 11 10
00
01
11
10
4
Four Variable Maps
F(A,B,C,D) = Σ(0,2,3,5,7,8,9,10,11,13,15)
CD
AB 00 01 11 10
00
01
11
10
5
Don’t Care Conditions
6
Don’t Care Conditions
F(w,x,y,z) = ∑ (1,3,7,11,15) +
d(w,x,y,z) = ∑ (0,2,5)
yz
F = yz + w’z
wx 00 01 11 10
00 X 1 1 X
01 X 1
11 1
10 1
7
Don’t Care Conditions
F(w,x,y,z) = ∑ (1,3,7,11,15) +
d(w,x,y,z) = ∑ (0,2,5)
yz
F = yz + w’x’
wx 00 01 11 10
00 X 1 1 X
01 X 1
11 1
10 1
8
Don’t Care Conditions (Example)
F(w,x,y,z) = ∑ (0,1,2,4,5) +
d(w,x,y,z) = ∑ (3,6,7)
yz
wx 00 01 11 10
00 1 1 X 1 F = w’
01 1 1 X X
11
10
9
NAND implementation
10
NAND Implementation
Two Graphic Symbols
x x x’+y’+z’ = (xyz)’
y (xyz)’ y
z z
AND - Invert Invert - OR
12
NAND – Two Level Implementation
1. (Simplified) Equation must be in Sum-of-Products form. (Two Levels)
13
NAND – Two Level Implementation
Example
F(x,y,z) = Σ(1,2,3,4,5,7)
1. Step-1: Simplify and express it in Sum of Products form
Use K-Map to simplify and convert into sum-of-product form
F = xy’ + x’y + z
2. Draw an AND-OR diagram
14
Multilevel NAND Circuit
If three or more levels in the equation, follow these steps.
15
Multilevel NAND Circuit
Example:
F = A(CD + B) + BC’
Step-1: Draw AND-OR Diagram
16
Multilevel NAND Circuit
Examples
F = (AB’ + A’B)(C + D’)
17
NOR Implementation
18
NOR Implementation
Two Graphic Symbols
x x x’.y’.z’ = (x+y+z)’
y (x+y+z)’ y
z z
19
NOR – Two Level Implementation
1. Equation must be in Product-of-Sum form. (Two Levels)
20
NOR – Two Level Implementation
Example
F= (A + B)(C + D)E
21
Multilevel NOR Circuit
If three or more levels in the equation, follow these steps.
22
Multilevel NOR Circuit
Example:
F = (AB’ + A’B)(C + D’)
23
Selected Problems
24
Problem 3-16: Simplify the following expression and
implement with two-level NAND circuit
F = AB’ + ABD + ABD’ + A’C’D’ + A’BC’
Step-1: Simplified circuit be in SOP form
F = A + BC’ + C’D’
CD
AB 00 01 11 10
00 1
01 1 1
11 1 1 1 1
10 1 1 1 1
25
Problem 3-16: Simplify the following expression and
implement with two-level NAND circuit
Step-1: Simplified circuit be in SOP form
F = A + BC’ + C’D’
Step-2: Draw AND-OR Diagram
00 0 0 0 0
01 0 1 0 1
11 0 0 0 0
10 0 1 0 1
28
Problem 3-22: Convert the following logic diagram into
multiple-level NAND circuit
D'
1 2
Z
D 1
3
CD 1
C 2
2
3
Y
1
3 1 2
2
(C+D)'
C+D 1
3
B 2
2
3
X
1
3
1 2 2
1
3
2
1
3
W
A 2
29