UMC Register Model

gotchas
-Sumanth Kedilaya
AXI interface
• 5 channels
• Read Address Channel- (ARx)
• Read Data Channel- (Rx)
• Write Address Channel- (AWx)
• Write Data Channel- (Wx)
• Write Response Channel- (Bx)
• Every channel’s transcation has an ID and can be used to match
request and response. Example- {ARID, RID}, {AWID,WID,BID}
AXI interface
• There are 2 AXI interfaces for each UMC.
• AXI Slave interface – named SmnTarg_*
• AXI Master interface- named SmnInit_*
• AXI Slave interface-> UMC is the slave and only responds to requests.
UMC cannot initiate any requests here. This will be driven by the CS.
This is used to access UMC, RSMU and PHY registers. Indirect
accessed registers;ApbDat and ApbCmd
• AXI Master interface-> UMC is the master and initiates via the RSMU a
read or a write. This is used to signal vwire activity to the pie registers
in DF, to read from Fusestrap and to fuse values in UMC etc.
AXI interface
• 2 ways to create transaction on AXI interface
• Create AXI packets and run on AXI interface using the sequencers provided by
AXI UVC. More complicated and try to avoid. Eg: csr_irritator
• Regmodel: The regmodel is effectively a big data structure and can be used
along with the AXI UVC to create transactions.
• For example: write() function in the RAL model uses the reg2axi() function in axi_adapter
to convert register data (Address, write data etc) into AXI bus protocol and uses the AXI
write data drivers to drive on to the AXI bus. Similarly for reads.
RSMU
• Where do we use RSMU?
• Getting in and out of reset.
• Writing into RSMU_UMC_COLD_RESETB and RSMU_UMC_HARD_RESETB registers
• Look at. src/verif/seqs/base/umc_reset_seq_libsvh:: hardresetb_deassert_sequence() and coldresetb_deassert_sequence()
• Loading fuse values
• Read from fuse strap via the AXI master interface. Load to UMC via UMCSMN.
• Look at src/verif/export/umc_reset_uvc/umc_reset_seq_lib.svh::fuse_delivery_seq()
• AEB security protection
• Set AEB_019 bit, which disables debugbus.
• Look at src/verif/seqs/axi/umc_csr_seq_lib.svh::rsmu_security_slave_check_seq()
• Power gating
• PGFSM-> Raven feature.
• As a traffic cop for UMC register access.
• Decode the AXI bus data, make it understandable to UMC and pass the traffic along for UMC to decode and execute (Read/Write)
src/verif/export/umc_reset_uvc/umc_rsmu_uvc.svh
• Where is RSMU in the umc depot? src/verif/export/umc_reset_uvc/umc_rsmu_uvc.svh
Register Model: What is it?
• A singleton data structure which mirrors the value of RTL registers, also used to
access the RTL registers via Frontdoor or backdoor.
• Why singleton? Because we want uniform data across all verif components.
• Where is it in our depot?
src/verif/export/umc_reg_singleton/umc_reg_singleton.svh
• Structure of a generic UVM RAL model.
• Uvm_reg_block -> register blocks which contain many registers like umcch, umcctrl
• Uvm_reg_map -> umchdec,umcctrldec which has register mapped on to it.
• Uvm_reg -> Individual registers like DramTiming1, BeqCtrl1 etc
• Uvm_reg_field -> each uvm_reg is divided into many register fields like Tcwl, Tcl etc.
Register Model: How does it look?
uvm_reg_block
Umc_w_phy_block

uvm_reg_block uvm_reg_block
Umc0 Umc1
(uvm_reg_map- (uvm_reg_map-
>GpuF0Map) >GpuF0Map)

uvm_reg_block uvm_reg_block
UMCCH0 UMCCTRL
UMCCH0 UMCCTRL
(uvm_reg_map-> (uvm_reg_map-
umcchdec) >umcctrldec)

uvm_reg
uvm_reg
Dramtiming1
ApbDat register
register

uvm_reg_field Uvm_reg_field uvm_reg_field Uvm_reg_field

Tcl[5:0] Tras[14:8] Trcdrd[21:16] Trcdqr[29:24]
Register Model: How do we use it?
• Various tasks in the object. Here are the main ones:
• Csr_write_reg() -> update both RTL and mirror values of entire register by either F/D or B/D
• Csr_read_reg() -> Read RTL values by either F/D or B/D, compares with mirror values. Errors if not
same*.
• Csr_write_reg_mirror() -> Update mirror value of register
• Csr_read_reg_mirror() -> Read mirror value of register
• Csr_write_field() -> update both RTL and mirror value of field by either F/D or B/D. Note:
UMCSMN is not designed for access of individual field. What this task does is, it accesses the
entire register and does a masked operation on the field.
• Csr_read_field() -> Read RTL values, compare with mirror values. Error if not same*
• Csr_read_field_mirror()-> Read mirror value of the field.
* set_volatile() -> set a field to be “volatile”, and it will skip the checking for consistency between
RTL and mirror value during reads. Generally done when dealing with hardware updated fields. Ex:
umc_uvc_env.svh::create_reg_model()
Register Model: Backdoor access
• How is backdoor access different from “Force”?
• Well, its not. RAL backdoor access just deposits the value into the register
more elegantly.
• We set up the “HDL” path to the register flop and deposit the value there.
This HDL path is nothing but the RTL hierarchy that we see in waves to the
signal.
• This is done using the set_hdl_path() in umc_reg_singleton.svh.
• Most of the registers have a standard path, but there are a few exception,
especially the ones which have an external driver apart from the SMN.
UMC register special features
• UMCCH Broadcast writes
• Write into a register instance of all the UMCCH. For example: Broadcast write
to Dramtiming0 in GNL would mean, in same time a single write would take to
a single register, write to all the umcch’s of a UMC instance.
• How is this done? Set REG_ADDR[14:12] = 1
• This is a tricky feature for the register model as broadcast is not a RAL feature
but a UMC architecture feature.
• You cannot create broadcast writes using the regmodel. We have to use the
AXI packet way of doing things.
• If register is written, we have a task monitoring the AXI interface in the
csr_monitor, which will update the register model values for all UMCCH’s
UMC register special features
• Shadow Writes
• There are cases in UMC, when the master register copy lies in UMCCH and
the shadow copy lies in UMCCTRL. Instead of doing 2 writes, 1 for each of
these registers, we specify the register has a shadow copy in a param file, and
the shadow copy will automatically get updated in RTL.
• Again, this is not a RAL feature but a UMC architecture feature. We update
the mirror value using the update_shadow_reg() in umc_reg_singleton.svh.
There is no indication in the RDL or RAL if a register has a shadow copy.
Hence, for now, we have to manually add registers into this list based on the
param file.
• The param file is in :
src/meta/registers/variant/umc*_0/master_shadow_spreadsheet.csv
Q&A