GAYATRI VIDYA PARISHAD COLLEGE FOR DEGREE & P.G.

COURSES (A)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING      
ENGINEERING AND TECHNOLOGY PROGRAM
RUSHIKONDA, VISAKHAPATANAM-530045 | WEBSITE: www.gvpcdpgc.edu.in
(Approved by A.I.C.T.E | Affiliated to Andhra University)

DESIGN OF LOW-POWER SRAM CELL

UNDER THE GUIDANCE

TEAM MEMBERS
Mr. S. Venkatesh M. Tech
Tammaneni Navya (5191421044)
Assistant professor,
Lanka Prasanna Kumar (5191421026)
Department of ECE
Saidala Sandhya (5191421040)
Kota Ramesh babu (5191421024)
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CONTENTS

 ABSTRACT
 INTRODUCTION TO MEMORY
 DESIGN OF 6T SRAM CELL
 OPERATIONS OF SRAM CELL
 CONVENTIONAL 6T SRAM AND LAYOUT OF 6T SRAM
 INVERTER CIRCUIT
 LECTOR TECHNIQUE AND LAYOUT
 DLP TECHNIQUE AND LAYOUT
 BASE PAPER
 REFERNCE

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ABSTRACT

As we observe, with the evolution of technology, devices are scaling down from time to time, which
leads to a reduction in the length of the channel of the MOSFET, giving importance to the speed of
operation. The processor required a new type of memory referred to as “cache memory” to keep
frequently used data and faster on-chip memory. SRAMs matched the performance. A wide range of
Microelectronics, multimedia, and System on Chip applications, SRAMs continue to be a crucial
component. To meet the performance requirement SOC applications and processors demand more
on-chip memory. Nowadays, SRAM is a universally used memory technology. Low power, fast
access SRAM is very much needed for system-on-chip (SOC) technologies. So in this project, we
will design a low power SRAM cell. The tool used for designing SRAM cell is Tanner Tool which
operates at 45nm, 90nm and 180nm technologies.

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INTRODUCTION TO MEMORY

 Computer memory is any physical device

capable of storing information temporarily,
like RAM (random access memory), or
permanently, like ROM (read-only
memory). 
 RAM is subdivided into two types SRAM
and DRAM.

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WHY SRAM
 SRAMs have been primarily designed for fulfilling the
below main requirements

1. To provide a direct interface with the CPU.

2. To transfer data at higher speeds than DRAMs cannot

achieve.

3. SRAMs take place in those systems which need low

power consumption.

4. It need not require periodical refreshments like DRAM.

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DESIGN OF 6T SRAM CELL

 The NMOS access transistors (M5 and M6)

located at the ends of the circuit and a pair of
cross-coupled inverters constitute a memory cell.
The NMOS elements (M3 and M4) of the latch are
the driver transistors, while PMOS (M1 and
M2)are the pull-up transistors.
 It can operate in three different modes

a. Read operation
b. Write operation
c. Hold operation

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READ OPERATION

Read operation when the bit line is 0 Read operation when the bit line is 1

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DESIGN OF CONVENTIONAL 6T SRAM IN 180NM FOR WRITE 1
OPERATION

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LAYOUT OF CONVENTIONAL 6T SRAM

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POWER ANALYSIS OF SRAM USING CONVENTIONAL 6T IN
180NM FOR WRITE 1 OPERATION

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INVERTER CIRCUIT

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RESULT

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DESIGN OF SRAM USING LECTOR TECHNIQUE IN 180NM FOR WRITE 1
OPERATION

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LAYOUT OF LECTOR TECHNIQUE

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POWER ANALYSIS OF LECTOR TECHNIQUE IN 180NM FOR WRITE 1
OPERATION

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DESIGN OF SRAM USING DLP TECHNIQUE IN 180NM FOR READ 1
OPERATION

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LAYOUT OF DLP

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POWER ANALYSIS OF LECTOR TECHNIQUE IN 180NM FOR READ
1 OPERATION

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 POWER ANALYSIS IN DIFFERENT TECHNOLOGIES IN MICRO WATTS

Technique Hold 0 Hold 1 Write 0 Write 1 Read 0 Read 1

Conventional 6T 14.4 9.71 8.72 8.72 12.8 9.76

180 nm

Lector 8.85 4.71 7.35 7.35 9.4 4.56

DLP 6.23 3.02 4.69 4.69 6.46 3.58

Technique Hold 0 Hold 1 Write 0 Write 1 Read 0 Read 1

Conventional 6T 4.52 5.31 2.79 2.84 4.58 5.27

90nm

Lector 2.24 2.96 1.34 1.34 2.37 1.42

DLP 1.90 2.05 0.60 0.601 1.97 2.06

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POWER ANALYSIS IN MICRO WATTS FOR 45 NM TECHOLOGY

Technique Hold 0 Hold 1 Write 0 Write 1 Read 0 Read 1

Conventional 1.41 1.37 0.75 0.75 1.41 1.04

6T
Lector 0.70 0.37 0.44 0.44 0.73 0.37
DLP 0.48 0.42 0.41 0.41 0.51 0.42

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BASE PAPER

Low-Power SRAM Cell using LECTOR Technique by the “Indonesian Journal

of Electrical Engineering and Computer Science”.

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REFERENCES
1. Design of Read and Write Operations for 6T SRAM Cell by Journal of Engineering Science and
Technology.
2. Low Power Design of A SRAM Cell by IJRCCT.
3. Design of 6T SRAM by International journal of engineering research & technology (IJERT).
4. Choudhari, S. H., & Jayakrishnan, P. Structural Analysis of Low Power and Leakage Power
Reduction of Different Types of SRAM Cell Topologies. 2019 Innovations in Power and Advanced
Computing Technologies (I - PACT). 2019.
5. Shaik, S., & Jonnala, P. Performance evaluation of different SRAM topologies using 180, 90 and 45
nm technology. 2013 International Conference on Renewable Energy and Sustainable Energy
(ICRESE).

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