A HIGH PERFORMANCE VLSI FFT ARCHITECTURE

By M.Jaya Lakshmi 10B01D5705

Agenda

y Signal processing and telecommunication applications

require FFT implementations that can perform

y large size y low latency computations while exhibitinglow power

consumption

y computational tasks are executed either by y a single, high frequency embedded processor y using an Application Specific Integrated Circuit (ASIC).

contd
y Previous FFT architectures
y Fully unfolded FFT architectures y Cascade FFT topologies y Higher Radix techniques

y Advantages of present architecture compared to

previous

Analysis of RADIX-43 Algorithm

The linear index mapping is transforms into a 4D index mapping as follows

Accumulator

R4 Architecture

3 a.R4

Engine

Architecture

B. Architecture Performance
y This architecture realizes a 4096-point FFT, by cascading two successive R43 stages. An additional stage of R43 would result in a 256K-point y cascade FFT architectures requires 6- R22 or R4 stages to perform a 4K-point FFT or 9 stages for a 256K-point FFT y improved latency compared to the other casscade architectures because it requires data buffering only between the two R43 stages instead of 6 plain R4 stages. y unfolded FFT implementations require memory of size 4K62 (points, stages, dual bank) to perform a 4K-point FFT, while our proposed architecture requires only 1/3 of that memory.

Advantages
y 20% of logic area utilization y 25 % Blocks RAM utilization y Through the use of optimized CoreLib multipliers

components area reduced to to 13% of the total resources

Comparison to previous works

y Some implemented a 2K complex point FFT processor

performs at 76MHz and sustaines throughput of 2K points/26us. y Some implemented 1-D and 2-D FFTs of 1024-point FFT at 80 MHz, at a computation time of 68us. y Some implemented a 64-point Fourier transform chip, operates at 20 MHz with 3.85 us latency. y Comparatively, the architecture of the R43 processor presented in this work performs a 64 complex point FFT operating at the frequency of 200 MHz with a 0.32us latency.

conclusion
y very high operating frequencies and the low latencies

of both the FPGA and VLSI implementations y reduced data memory y improved multiplier utilization y occupying a smaller silicon area ,consuming less power compared to similar solutions

References
y A. Oppenheim, R. Schafer Digital Signal Processing , Prentice Hall

1975. y Clark D. Thompson Fourier Transform in VLSI , IEEE Transactions on Computers, 1983. y E.H. Wold and A.M. Despain Pipeline and Parallel FFT Processors for VLSI Implementations , IEEE Transactions on Computers, vol. C33, 1984. y J. Y. OH and M. S. Lim, New Radix-2 to the 4th Power Pipeline FFT Processor , IEICE Trans. Electron., VOL. E88-C, NO. 8, August 2005.

Thank u

Queries?