ECE 515

Design of 3D Integrated Systems

Lecture 23:
Mixed Signal Simulation using Cadence
AMS

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 AMS Design Configuration
 Cadence Virtuoso AMS is a mixed language, mixed signal
simulator
 Cells in the library typically have multiple views or
representations
E.g., schematic, symbol, Verilog, layout

 AMS configuration window allows you to easily

switch between schematic views for a block

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 AMS Configuration Window Setup
Views available for cell that can be used in simulation

We can use configuration view to select any of these views in simulation

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 Configuration Window
 This configuration mechanism gives designers a significant
freedom to take hierarchy design approach.

Source:
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 Configuration Window
 Example: Inverter
 We can first use inverter Verilog model which is a very abstract
model in simulation to save time
 Then, we use Verilog-A model which may contain certain
electrical characteristics of the inverter circuit in simulation
 Finally, we use transistor-level implementation which contains
more details in the design
// VerilogA for inverter Real vout_val;
Integer logic1;
`include “constants.vams” Analog begin
`include “disciplines.vams” logic1 = V (vin) > vtrans;
// Verilog HDL @ (cross(V(vin) – vtrans, 1)) logic1 =1;
// for inverter Module inv (vin, vout); @ (cross(V(vin) – vtrans, -1)) logic1=0;
Input vin;
Module inv (vin, vout); Output vout; Vout_val =(! Logic1) ? Vlogic_high ; vlogic_low;
Input vin; Electrical vin, vout;
Output vout; Parameter real vlogic_high = 5; V(vout) <+ transition ( vout_val, tdel, trise, tfall);
Parameter real vlogic_low = 0;
Assign vout=~vin; Parameter real vtrans = 2.5; End
Parameter real tdel = 0.1n from (0:inf);
endmodule Parameter real trise = 0.1n from (0:inf); endmodule
Parameter real tfall = 0.1n from (0:inf);
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 OSS/Irun Simulation
 OSS-based netlister reads simulation information and uses
irun for one-step flow.

 What is irun?
 1-step command to
compile, elaborate, and
simulate your design

 It is used exclusively in
the OSS netlister flow

 It can compile and

simulate Verilog, System
Verilog, VHDL, C, C++,
SPICE, etc.

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 OSS/Irun Simulation
 Simulation mode
 Batch
 Interactive

 If we select “batch”
mode, the simulation
looks like what we see in
ADE window

 If we select “interactive”
mode, simulation results
will be plotted in digital
simulator “SimVision”

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 AMS Simulation with SDF annotation
 How to simulate analog circuits with synthesized
gate-level Verilog block?
 We need to consider back annotation timing delays
 What is back annotation?
 The process of putting delays to the cells in a netlist
during netlist simulations is called back annotation.
Verilog description

Standard Cell Library Logic Synthesis

Netlist Place and Routing

SDF
Simulation Back Annotation

Results
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 AMS Simulation with SDF annotation
 What is SDF?
 Standard Delay Format
 An IEEE standard for the representation and
interpretation of timing data for use
 An efficient way for dynamic timing verification

After placement and routing, Encounter can

generate a final SDF file that includes both cell
and interconnect delays.

Source: 9
 An Mixed Signal Simulation Example

I2C Master I/O Pad Master I/O Pad Master I2C Slave
(Verilog Code) (Transistor Netlist) (Transistor Netlist) (Verilog Code)

Digital Domain Analog Domain Analog Domain Digital Domain

ESD, pad
capacitor, pull-up
resistors

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 AMS Simulation with SDF annotation
 A Design Example

I2C Master IOPAD

I2C Master (Verilog)

I2C Slave IOPAD

I2C Master (IOPAD) I2C Slave (Synthesized

gate-level Verilog)

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AMS Simulation with Synthesized gate-level Verilog

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 AMS Simulation Example
 Click “simulation” tab and select “Options” – “AMS
simulator”.

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 AMS Simulation Example
 Under the main page,
we need to include
two Verilog files
 I2C gate level
Verilog file
 Standard cell
library which is
used in synthesis
process
 At bottom of this page,
we need to type
“+define+NTC
+define+RECREM”,
which is used in timing
setup during AMS
simulation
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 AMS Simulation Example
 Then, we switch to “SDF”
tab, where we include SDF
command file for backend
timing annotation.

 SDF command file usually

consists of 4 lines
 The compiled SDF file
path
 Log file path A sample SDF_CMD_FILE is provided below.
 Back annotation scope // SDF command file sdf_cmd1
 MTM control COMPILED_SDF_FILE =
"dcmt_timesim_vhd.sdf.X",
SCOPE = :uut,
MTM_CONTROL = "TYPICAL",
SCALE_FACTORS = "1.0:1.0:1.0",
SCALE_TYPE = "FROM_MTM";
// END OF FILE: sdf_cmd
Source:
http://www.xilinx.com/support/answers/19447.html 15
 AMS Simulation Example
 Next, we setup the
Verilog timing options
 Delay mode: path

 Now we have setup all

options and ready to
start simulation.

 After we start
simulation, we need to
pay attention to the
Irun.log, which shows
possible error
messages and
progress.
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 AMS Simulation Irun.log
 For example, we can find the back annotation is
used in the simulation from the message “SDF
statistics: No. of path delays …
Annotated … 100%”

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 AMS Simulation Example
SimVision Simulation Control Window

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 AMS Simulation Example
SimVision Waveform Plot Window

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 AMS Simulation Example
Console of SimVision Simulator

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 AMS Simulation Example
SimVision Waveform Plot Window

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 AMS Fast Simulation
 Advanced Performance Options
 Mixed signal simulation is controlled, and limited by the analog
solution.
 The faster the analog solution, the faster the overall mixed
signal solution
 One way to speed up mixed signal simulation is to make
analog engine faster

 Virtuoso Accelerated Parallel Simulation ---APS

 Parallel Matrix, analog simulation up to 16 cores
 Full Spectre accuracy
 Performance increase is dependent on circuit size, activity,
content, and hardware platform
 A design with 50k Spice elements running in AMS-APS
can be 5-20X over AMS Spectre

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 AMS Simulation Example
Simulation speedup tricks: APS is Cadences latest
For this simulation time, multi-threaded spice simulator.

AMS only, conservative - 3 hours Watch this video for more details:
https://www.youtube.com/watch?v=StzINZ2Ocb8
AMS+APS, conservative- 30 minutes
AMS+APS, moderate 20 minutes

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 Reference
Cadence Virtuoso AMS Designer Workshop, Feb 2012

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