BI2001B - Diseño de sistemas de

bioinstrumentación digital
Sequential Logic circuits

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Combinational logic circuit 

 A combinational logic circuit is a circuit whose outputs only depend

on the current state of its inputs.

 In mathematical terms, each output is a function of the inputs.

 These functions can be described using logic expressions but is most

often (at least initially) using truth tables.

 Logic gates are the simplest combinational circuits. As we saw earlier,

their output is a very simple function of their inputs with a very simple
truth table. Naturally, the more inputs there are, the larger the truth
table

 Examples
• Decoders
• Demultiplexers
• Multiplexers
• Logic gates

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Sequential logic circuit 

 Sequential circuit is a combination of a combinational circuit and a

memory elements connected in feedback path.

 The memory elements are devices capable of storing binary

information within them.

 The binary information stored in the memory elements at any given

time defines the state of the sequential circuit.

 The sequential circuit receives binary information from external

inputs.
Asynchronous
 Thus, a sequential circuit is specified by a time sequence of inputs, sequential circuits 
Sequential logic
outputs and internal states circuit 
Synchronous
sequential circuits 

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Asynchronous sequential circuits 

 Asynchronous sequential circuits do not use clock signals as

synchronous circuits do.

 Instead, the circuit is driven by the pulses of the inputs which means
the state of the circuit changes when the inputs change.

 Also, they don’t use clock pulses. The change of internal state occurs
when there is a change in the input variable.

 Their memory elements are either un-clocked flip-flops or time-delay

elements. They are similar to combinational circuits with feedback

 The memory of the asynchronous sequential circuit include flip-flops

or time-delay devices

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Synchronous sequential circuits 
 Synchronous sequential circuits use clock signals

 Synchronous sequential circuits that use clock pulses in the inputs of

memory elements are called clocked sequential circuits.

 In synchronous sequential circuits memory elements are used like

clocked flip flop

 Due to the presence of clock pulse the operating speed of synchronous

sequential circuits is low. In these circuits change in state occurs in
response to clock pulse.

 Examples:
 counters,
 shift registers,
 memory units.

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

SR-type Flip-Flop
 SR Flip-Flop
 One-bit memory bistable device

• The SR flip-flop, also known as a SR Latch, can be

considered as one of the most basic sequential logic
circuit possible.

• This simple flip-flop is basically a one-bit memory

bistable device

We must comply that

 When “SET” is active, the device output = “1”,
labelled S and
 When “RESET” is active, the device output = “0”,
labelled R.

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 Set-state
Consider the circuit shown above.

If input logic level are

• R = “0”
• S = “1”

Output
• Q = “0”
•  = “1”.

 the NAND gate Y has at least one of its inputs at logic

“0” therefore, its output  must be at a logic level “1” A B X
(NAND Gate principles). 0 0 1
 Output  is also fed back to input “A” and so both 0 1 1
inputs to NAND gate X are at logic level “1”, and
1 0 1
therefore its output Q must be at logic level “0”.
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 Set-state
Consider the circuit shown above.

If the reset input R changes state, and goes HIGH, then,

• R = “1”
• S = “1”

Output
• Q = “0”
•  = “1”.

 NAND gate Y inputs are now R = “1” and B = “0”.

Since one of its inputs is still at logic level “0” the
output at  still remains HIGH at logic level “1” and A B X
there is no change of state. Therefore, the flip-flop 0 0 1
circuit is said to be “Latched” or “Set” with  = “1” 0 1 1
and Q = “0”.
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 Reset-state
Consider the circuit shown above.

If the reset input R goes HIGH and set to LOW, then,

• R = “1”
• S = “0”

Output
• Q = “1”
•  = “0”.

 As gate X has one of its inputs at logic “0” its

output Q must equal logic level “1” (again NAND
gate principles). A B X
 Output Q is fed back to input “B”, so both inputs 0 0 1
to NAND gate Y are at logic “1”, therefore,  = “0”. 0 1 1
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 Reset-state
Consider the circuit shown above.

If the set input, S now changes state to logic “1” with

input R remaining at logic “1”, then
• R = “1”
• S = “1”

Output
• Q = “1”
•  = “0”.

 Output  still remains LOW at logic level “0” and there A B X

is no change of state. 0 0 1
 Therefore, the flip-flop circuits “Reset” state has also 0 1 1
been latched with  = “0” and Q = “1”.
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 “set/reset” Truth table

A B X
0 0 1
0 1 1
Invalid because output is always HIGH
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 Switching Diagram

 The condition of S = R = “0” causes both

outputs  and Q to be HIGH together at logic level “1”
when we would normally want Q to be the inverse of .

 The result is that the flip-flop looses control of  and Q, and

if the two inputs are now switched “HIGH” again after this
condition to logic “1”

 The flip-flop becomes unstable and switches to an

unknown data state based upon the unbalance as shown in
the following switching diagram.

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 SR Flip-Flop
 Typical applications: 1-bit memory

 Makes computer memories possible

 Used in many sequential logic circuits
 Make up the basic form of this circuit whose output has two
stable output states.
 When the circuit is triggered into either one of these states by a
suitable input pulse, it will ‘remember’ that state until it is
changed by a further input pulse, or until power is removed
(thus called Bi-stable Latch)
 The SR flip-flop can be considered as a 1-bit memory, since it
stores the input pulse even after it has passed.
 Device is universal by using the most versatile NAND (most
widely used)

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

Clocked SR Flip-Flop
 Clocked SR Flip-Flop
Truth table

 A gated SR latch (or clocked SR Latch) can only change its

output state when there is an enabling signal (EN) along with
required inputs.

 That means the inputs can only act upon when the latch is
enabled otherwise there will be no change in output state even
required inputs are applied.

 In other words, the latch is active when ENABLE signal (EN)

EN S R Q   A B X
is HIGH
0 X X Memory Memory 0 0 1
 And it is inactive when ENABLE signal (EN) is LOW. 1 0 0 Memory Memory 0 1 0
1 0 1 0 1 1 0 0
 This HIGH LOW enable signal (EN) is applied to the gated 1 1 0 1 0 1 1 0
latch in the form of clocked pulses 1 1 1 Unstable Unstable
X means “don’t care”, a “0” or a “1”
Unstable because output is always LOW

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

D-type Flip-Flop
 D-type Flip-Flop
One-bit memory device

 One of the main disadvantages of the basic SR NAND Gate

Bistable circuit is that the indeterminate input condition of
SET = “0” and RESET = “0” is forbidden

 Thus, the D-type flip-flop is a modified Set-Reset flip-flop

with the addition of an inverter to prevent the S and R inputs
from being at the same logic level

 D-type Flip Flop is by far the most important of all the

clocked flip-flops.

 By adding an inverter (NOT gate) between the Set and Reset

inputs, the S and R inputs become complements of each
other ensuring that the two inputs S and R are never equal (0
or 1). This allows the user to control the inputs using one
single D (Data) input

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 D-type Flip-Flop
Truth table

Clk D S R Q Description

0 X 0 0 Q Memory

1 0 0 1 0 1 Reset Q = 0

1 1 1 0 1 0 Set Q = 1

X means “don’t care”, a “0” or a “1” A B X

0 0 1
0 1 1
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

D-type Flip-Flop Applications
 D-type Flip-Flop
Data storage

 In digital circuits the data is normally stored as a group of

bits, represented in numbers and codes.

 So, it is easy to take data on parallel lines and store the data
simultaneously in a group of flip flops, arranged in a
particular order.

 Registers are the basic multi – bit data devices.

 They are formed by connecting number of D flip – flops such

that multiple bits of data can be stored

 Each D flip – flop is connected with a respective data input.

Clock input applied is same to all the flip – flops so that all
of them will store the data simultaneously from their
respective D inputs when a positive edge triggered clock
signal is applied

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 D-type Flip-Flop
Data transferring as shift registers

 D flip – flops are also widely used in data transfer.

 For transferring the data, D flip – flops are connected to form

a shift register.

 A cascade connection of D flip – flops with same clock

signal will form a shift register.

 A shift register can shift the data without changing the

sequence of bits.

 When a clock pulse is applied, the one bit data is shifted or

transferred. Shift registers can store the data temporarily

 4-bit storage shift register using D flip flop is shown

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 D-type Flip-Flop
Frequency Division

 This is the most important application of D Flip Flop. In

Frequency Division circuits, the state output of the D flip
flop (Q’) is connected to the Data input (D) as a closed
feedback loop. Two successive cock pulses will make the flip
flop to Toggle, for every two clock cycles.

 As the name implies, the frequency divider circuits are used

to produce the digital signal output exactly half the input
frequency. The frequency divider circuits are generally used
in design of asynchronous counters

 The operation of the circuit is very simple. The incoming

data signal is clocked by the clock input signal. The circuit
will perform the division of the input frequency by using the
feedback loop i.e. connected to the Data input from Q’. The
frequency divider circuit divides the input frequency by 2 for
every two clock pulses

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

Asynchronous Counter by D-type Flip
flop
 Asynchronous Counter
Logic circuit, edge triggered device

 The D flip-flop is an edge triggered device which

transfers input data to Q on clock rising or falling
edge.

 D flip flop is as a Data Latch. A data latch can be

used as a device to hold or remember the data
present on its data input, thereby acting a bit like a
single bit memory device

*changes state (toggle)

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Asynchronous Counter
Logic circuit, Falling edge-triggered

 FF0 acts upon the clock frequency signal

 FF1 acts upon the output and so on

 The output (LSB) changes its state (toggle) at

each negative transition of the clock.

 The output  changes state (toggle) every timegoes

from HIGH to LOW because  acts as the clock
input for FF1.

 of each FF is feedback to D which affects and that

toggles when changes from HIGH to LOW
*changes state (toggle)

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Asynchronous Counter
Falling edge-triggered Time diagram
Clk D S R Q Description
A B X
0 X 0 0 Q Memory
0 0 1
(remembering
0 1 1 previous signal)
1 0 1 1 0 0 1 0 1 Reset Q = 0
1 1 0 1 1 1 0 1 0 Set Q = 1

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 Clk D S R Q Description
Q1
D1 0 X 0 0 Q Memory
S1 (remembering
R1 previous signal)
clk 1 0 0 1 0 1 Reset Q = 0
Q0 1 1 1 0 1 0 Set Q = 1
D0
S0 A B X
R0
0 0 1
clk
0 1 1
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics

 1 1 0 0 1 Clk D S R Q Description
Q1 0 0 1 1 0
D1 1 1 0 0 1 0 X 0 0 Q Memory
S1 1 1 0 0 1 (remembering
R1 0 0 1 1 0 previous signal)
clk 0 1 0 1 0 1 0 0 1 0 1 Reset Q = 0
1 0 1 0 1
Q0 0 1 0 1 0
1 1 1 0 1 0 Set Q = 1
D0 1 0 1 0 1
S0 1 0 1 0 1 A B X
R0 0 1 0 1 0 0 0 1
clk 1 1 1 1 1 0 1 1
1 0 1
1 1 0

Prof. Dr.-Ing. Diego Luján Villarreal, Department of Mechatronics