BEEDEE716-VLSI DESIGN

UNIT-1 INTRODUCTION

• Evolution of IC technology • CMOS Inverter

• MOS and VLSI Technology a) Design parameters,
• Basic MOS Structure b) DC characteristics,
a) Basic MOS transistors operation c) Noise Margin,
b) Enhancement mode, d) Switching characteristics
c) Depletion mode, e) Inverter time delay,
d) static and dynamic behavior,
f) Power dissipation-static and
• Basic CMOS technology dynamic power dissipation,
a) p well, n well,
b) twin tub,
• NMOS inverter.
c) SOI
d) BiCMOS technology.

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 CMOS inverter

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 CMOS inverter

• Comprises both PMOS

and NMOS.
• PMOS body is tied to Vdd,
NMOS source is tied to
GND. (No floating body)
• Vin: Gate terminals of
PMOS and NMOS
• Vout: from drain terminals of
PMOS and NMOS

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 Various regions of operation

• Vtn(Vtp) is the threshold voltage of the n(p)-channel

device.
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 DC transfer characteristics
• A plot between Vout and
Vin.

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 Switching activity

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 Propagation delay

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 • In general, there are 4 timing parameters.
• Rise time (tr) is the time, during transition, when
output switches from 10% to 90% of the maximum
value.
• Fall time (tf) is the time, during transition, when
output switches from 90% to 10% of the maximum
value.
– Many designs could also prefer 30% to 70% for rise time
and 70% to 30% for fall time.

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 • The propagation delay high to low (tpHL) is the
delay when output switches from high-to-low, after
input switches from low-to-high.
• The delay is usually calculated at 50% point of input-
output switching.
• Now, in order to find the propagation delay, we need
a model that matches the delay of inverter.
• The switching behavior of CMOS inverter could be
modeled as a resistance Ron with a capacitor CL, a
simple first order analysis of RC network will help us
to model the propagation delay.
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 Our aim is to find 't' at Vdd / 2.
Vout = (1-e^-(t/τ)) Vdd,
where τ = RC = time constant.

Substituting 'Vout' equal to Vdd/2, and 't'

equal to 'tp' in above equation, we get
the following :

Vdd/2 = (1-e-(tp/τ)) Vdd

Therefore, tp = ln(2)τ = 0.69τ

Hence, tp = 0.69RC

Hence, a CMOS inverter can be modeled

as an RC network, where
R = Average 'ON' resistance of transistor
C = Output Capacitance

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 For any queries:
mubarakali@sastra.ac.in
WhatsApp : 9791715927

Thank you…