Architecture of 8085

Microprocessor
Features of 8085
• Power-down mode
• Low power dissipation
• Single power supply +3V to +6V
• Operating temperature from -40 to +85 deg C
• On-chip clock generator
• Four vectored interrupts
• Serial input/serial output port
• Addressing capability to 64K bytes of memory
• Available in 40-pin plastic DIP package.
Architecture of 8085
Architecture of 8085
• Memory and I/O control Lines:
 R/W, IO/M, Ready/Wait, ALE
 Status Lines, Address Lines, Data Lines

• CPU and Bus Control Lines:

 Reset, Interrupts,
 Bus Request/Bus Grant Lines.

• Utility Lines:
 Clock, I/O Lines
 Power Supply Lines.
8085
• 8085 Hardware Model:
8085
• 8085 Programming Model:
Bus structure of 8085 microprocessor
Operations performed by ALU
• Addition
• Subtraction
• Logical AND
• Logical OR
• Logical Exclusive OR
• Complement
• Increment/decrement by 1
• Rotate left, rotate right
Registers
• Flag Register
Example
• Eg1. Determine the status of different flags
after addition of 07H and CFH
• 07H -> 00000111B
• CFH-> 11001111B
• Sum=11010110B, Cy=0, Ac=1, P=0, S=0, Z=0
• Eg2.Determine the status of different flags
after addition of CEH and 9BH
System Bus: Address, Data &
Control
 Timing and Control Unit
• Coordinates and control the subsystems within
the CPU and also outside CPU.
 Hardwired,
 Micro-programmed.
Definitions:
• Instruction Cycle: Time required to execute an instruction.
– Range: 1-Machine cycle to 5-Machine cycles

• Machine Cycle: Time required to complete one operation of

accessing memory, accessing I/O devices or sending an
acknowledgement.
– Range: 3 T-states to 6 T-states

• T-State: It is a subtask performed in one clock period.

 Instruction Execusion
• IC = FC + EC

• EC = Read Cycle(s) and/or Write Cycle(s)

Types of Mechine Cycles:
• Opcode Fetch M.C. – Fetch –> 4T (3T-fetching+1T-decoding)
• Memory Read M.C. – Read –> 3T
• Memory Write M.C. – Write –> 3T
• I/O (Input/output) Read M.C. – I –> 3T
• I/O (Input/output) Write M.C. – O –> 3T
Timing diagram for OPCODE FETCH
Timing diagram for Memory Read
Timing diagram for Memory Write
 Pin Diagram of 8085 M.P.:
• A15 – A8 (output, 3-state):

• AD7 – AD0 (input/output, 3-state):

• ALE (output) Address Latch Enable:

• S0 , S1 , IO/M (output):