Basic Computer Organization

Ms. Vaishali g. Powar

Evolution of Computer
Mechanical Era
Electromechanical Era
Electronic Era
VLSI Era
 Mechanical Era
A mechanical computer is built
from mechanical components such as levers and gears
Babbage’s Difference Engine
Analytical Engine
 Mechanical Era
Babbage’s Difference Engine
Created by Charles Babbage a “father of computing”
Created the difference engine to compute mathematical
tables more accurately
It is used as prototype
He designed another engine, difference Engine 2
It was incomplete :fabrication of 4000 mechanical parts
 Mechanical Era
Analytical Engine: Created by Charles Babbage
The first general purpose computer

IO •Compiled mathematical
Main equipm
ALU tables using add, subtract,
memor ents(pri
(the polynomial functions
y(the nter &
mill)
store) card •Programs are written using
punch
punched cards
•Stiff paper that holds
commands
Operation Variable
•Commands and data are
Cards Cards indicated by holes/no holes
•Punched cards were used
to Input commands
Limitations of Mechanical Computers
Limited speed: Inertia/friction of moving components
Complex and unreliable:data movement using liner
and gears
Electronic Era
Processing and storage of digital signals with
electronic devices is very high
Development of electronic devices like vacuum tubes
and transistors resulted in the generation of electronic
computers
1st Generation
2nd Generation
3rd Generation
4th Generation
5th Generation
Electronic Era:1st Generation
1951 – 1959
Based on Vacuum tubes
Vacuum tubes: Control electric current using the
vacuum, and used to start/stop, or change the flow
based on the current
1. Harvard Mark 1
2. ENIAC
3. EDVAC
4. UNIVAC
Electronic Era:1st Generation
 Harvard Mark 1
A electro-mechanical computer
Created by Howard Aiken and Grace Hopper
Developed and built by IBM
Could store 72 numbers
Multiplication took 6 seconds
Used in WW II to compute artillery tables
Produced Mathematical
Tables
Harvard Mark 1
Electronic Era:1st Generation
 ENIAC
First electronic general purpose computer
Created at the University of Pennsylvania
Cost almost $500,000 (approx. $6,000,000 today)
One of first programs a study of the hydrogen
bomb
A secret military project designed to improve the
construction of artillery firing tables
Electronic Era:1st Generation
 ENIAC
Set of accumulators : capacity of twenty 10 digit
decimal numbers
10 bit ring counter stores a number:9=0000000001
Programmed by plugging and unplugging cables and
master program was manually set
Results were punched on cards
Harvard mark I and ENIAC stores program and data in
separate memories
ENIAC
Electronic Era:1st Generation
EDVAC
Proposed by Von Neumann in 1945 and incorporates
the concept of stored program
Enables program to modify its own instruction
Serial processing of data
Main memory:1024 words
Secondary memory: 20K words
Instruction format: A1 A2 A3 A4 OP
 Electronic Era:organiztion of 1st G computer

Central
processing
Instructio Unit(CPU)
Program
n
Control Input Output
Main Memory Equipments
Program,d Secondary
(Program and data
ata,operato memory,keyboard,
for execution)
r,command printer,etc.
s
Data Data
Processing
IAS Computer
IAS Computer
Developed at Institute of Advanced Studies in Princeton
by Von Neumann in 1947
Main Memory: 4K words
Secondary Memory: 16K words
Basic Unit of information : 40-bit word
Instruction : 20-bit word
Number system : signed binary fraction, integers
Instruction format: OP A
OP : 8-bit opcode
A : 12-bit operand address
IAS Computer
CPU has small set of high speed storage devices called
registers
Special register Accumulator is used to store operand
and result
Next instruction address is calculated by incrementing
address of current instruction.
Special register Program Counter is used to store
address of the current instruction
IAS Computer : Instruction Set
Types of instruction
1. Data Transfer
2. Data Processing
3. Program Control
 Instructions are represented by HDL or RTL
 Instruction is fetched and executed in several steps
 All steps form instruction execution cycle
 2 instructions are fetched in single cycle
Limitations of IAS computer
Writing and debugging self modifying program is
difficult and error prone
Small storage space in CPU, results in high traffic in
CPU and MM and programs are lenghty
No procedure call and return statemnts
Non numerical task are difficult to write and executed
slowly
Limited IO instructions
Electronic Era:2nd Generation
1959-1965
Based on Transistors
Input :punch cards, Output : printers
Computers became smaller, cheaper, more reliable,
and efficient
Transistors work as switches on current, turning it on
or off (like binary 0 or 1).
Transistor generates a lot of heat, but less than vacuum
tubes
Stored instructions in memory
Electronic Era:2nd Generation
Special register is provided to hold an index and facilitate data
and address manipulations
Introduced floating point number format and supporting
instructions
IO processor was used to execute IO tasks so that CPU and IO
tasks can be simultaneously executed
Introduced high level programming language.
Compilers were used to translate high level language program
into machine language
Operating Systems are developed to manage resources and to
provide services to users
Supports multiprogramming
Electronic Era:3rd Generation
1965-1971
Used Integrated Circuits
Input : Keyboards instead of punch cards
Output: Monitors for display
IC: Small chips containing thousands of transistors
Electronic Era:3rd Generation
IBM System/3pes60 is standardized computer in this
generation
200 instruction types
Many addressing modes and data types
16 general purpose registers are provided as internal storage
Smallest unit of information for data transmission and
storage: 8-bit( byte)
CPU states:
1. Supervisor state: used by operating system
2. User state : used for executing application programs
 Status register(SR): used to store program status
word(PSW)
Electronic Era:3rd Generation
1. Architecture :
Structure and behavior seen by assembly language
programmer
Includes instruction set, data formats, addressing
modes and general design of CPU, main memory and
IO subsystem
2. Organization :
 Logical and physical design techniques used to
realize the architecture
 VLSI Era
1960- present
Designed around ICs
IC is electronic circuit composed of transistors manufactured on
chip of semiconductor material
IC is mounted into protective plastic or ceramic package
It provides electric connection points(pins) for connection
A multichip module is a package containing several IC chips with
electric connections between the chips
IC density: No of transistors contained in the chip
Based on density of transistors ICs are classified as:
1. SSI : less than 100 transistors
2. MSI : hundreds of transistors
3. LSI : thousands of transistors
4. VLSI : millions of transistors
 VLSI Era
IC Families:
1. Bipolar : use both negative and positive carriers
2. Unipolar (MOS): NMOS-negative carriers
PMOS-positive carriers

 Processor Architecture
1. Mainframe Computer
2. MiniComputer
3. MicroComputer
CPU Organization
Primary Function: To execute sequence of instructions
stored in an external main memory
Program execution :
1. CPU transfers instructions and operands fromm main
memory to registers
2. CPU executes the instructions in sequence
3. If necessary , the CPU transfers results to main
memory
CPU Organization : External Communication
Instructions
Main
CPU Data
Memory
MM

Processor-Memory Communication without Cache

Instructions Instructions
Cache Main
CPU Data Memory Data Memory
CM MM

External Memory M

Processor-Memory Communication with Cache

CPU Organization : External Communication

CPU communicates with external memory using address of

the memory location address.
Memory location with address adr is referred as M(adr)
CPU communicates with IO devices by using addressable
registers called as ports
IO communication:
1. Memory – mapped IO: memory locations and IO devices
share same address space
No IO instructions
2. IO –mapped IO : memory locations and IO devices use
different address space
Special IO instructions for IO read and write
CPU Organization : CPU Modes
 Programs executed on general purpose computer:
1. User programs: handles specific application
2. Supervisor programs : part of operating system that
handles various routine aspects of computer system
 Interrupt service is supported by CPU to receive the
request for supervisor services directly from SM and
other IO devices
 To handle interrupt CPU suspends current task and
transfer control to ISR
CPU Organization : CPU Operation

Begin Execute the

Instruction

Instruc Interru
No tion No pts
waiting waiting
? ?

Yes Yes

Fetch the next Transfer to ISR

instruction
Accumulator based CPU
Instruction Control
Decoder Signals

IR AR PC

PCU

To M and IO System Bus

Devices

DR AC

Arithmetic
Logic Unit

DPU
Accumulator based CPU
Instruction set:
Type Instruction HDL Format Assembly
Format
Data transfer Load AC:=M(X) LD X
Store M(X):=AC ST X
Move register DR:=AC MOV DR,AC
Move register AC:=DR MOV AC,DR
Data Add AC:=AC+DR ADD
Processing
Subtract AC:=AC-DR SUB
And AC:=ACandD AND
R
Not AC:=not AC NOT
Program Branch PC:=M(adr) BRA adr
Control
Branch zero If AC=0 then BZ adr
PC=M(adr)
Types of Instruction
Instruction consists of
1. Operation field that specifies the operation to be performed
2. Address field which contains the location of the operand
3. Mode field which specifies how operand value is specified
Instruction length varies depending on addresses used in the
instruction .
CPU organization is of three types based on the number of
address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
Intruction types based on number of
addresses
One address
Two address
Three address
Zero address
One address Instruction

Example: X = (A+B)*(C+D)

LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X
Two Address Instruction

Example: X = (A+B)*(C+D)

MOV R1, A
ADD R1, B
MOV R2, C
ADD R2, D
MUL R1, R2
MOV X, R1
Three Address Instruction

Example: X = (A+B)*(C+D)

ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
Zero Address Instruction

Example: X = (A+B)*(C+D)

PUSH A
PUSH B
ADD 
PUSH C
PUSH D
ADD 
MUL
POP X
Data Representation
Information

Data Instructions

Non-
Numbers Numerical data

Fixed Floating
Point Point

Bina Dec i Bina Dec i

ry mal ry ma l
Floating Point Number format
It is used to represent very large and very small numbers
It can represent positive and negative number
Floating point number is represented by scientific notation:
N= M*B^E
where M: Mantissa
B: Base
E: exponent
 Decimal number system uses B=10 and Binary number
system uses B=2

Floating Point Number format
Representation of floating point number is not unique.
32.86 can be represented
as 3.286×10^1, 0.3286×10^2, 0.03286×10^3
To get unique presentation, the fractional part is in its
normalized form
It is normalized by adjusting radix point position such
that, there is only a single non-zero digit before the radix
point
Adjusting exponent:
moving radix point to left, increment exponent
moving radix point to right, decrement exponent
Floating Point Number format
Example:
M,E: 3- Bit signed integers then
M and E ranges between -3 to 3
smallest nonzero positive number is (001,111)
=1*2^-3
= 0.125
Normalization and biasing
Each represent able number must have unique or
normal form in floating point number system
An unnormalized number is normalized by shifting the
mantissa to the right or left and approximately
incrementing and decrementing the exponent to
compensate the mantissa shift
Normalization and biasing
Representation of zero:
0*B^E=0 but round off errors result in mantissa
nearly , but not exactly ZERO
So E must be largest negative number i.e. –K
k-bit exponent: -2^(k-1) to 2^(k-1)-1 OR
-2^(k-1)+1 to 2^(k-1)
Representing zero by sequence of zeroes will have
same form in both fixed point and floating point
So exponent is represented in excess-K code format
where K is bias
IEEE 754 standard
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Mantissa

S: sign bit (0 :non-negative, 1: negative)

Normalize significand: 1.0 ≤ |significand| < 2.0
Significand is Fraction with the “1.” restored
Always has a leading pre-binary-point 1 bit, so no need to represent it
explicitly (hidden bit)

Exponent: excess representation: actual exponent + Bias

Ensures exponent is unsigned
Single precision: Bias = 127;
Double precision: Bias = 1203
IEEE 754 standard

N= (-1)^S * 2^(E-127) * 1.M

If E=255 and M!=0, then N= NaN

If E=255 and M=0, then N= infinity
If 0<E<255 then N= (-1)^S * 2^(E-127) * 1.M
If E=0 and M!=0, then N= (-1)^S * 2^(E-126) * 0.M
If E=0 and M=0, then N= (-1)^S * 0
IEEE 754 standard : Example

Represent –0.75
Convert 0.75 into binary
Normalize M
Adjust Exponent and bias it
0.75=0.11
S = 1
Fraction = 1000…002
Exponent = –1 + Bias
Single: –1 + 127 = 126 = 011111102
Double: –1 + 1023 = 1022 = 011111111102
RISC architecture
Reduced Instruction Set Computer
Load and Store Architecture
Fixed length short instructions
Few instruction types and addressing modes
Easily decoded instruction format
Fast single cycle instruction execution
Hardwired control unit
Use of compilers to optimize object code performance
ARM6
CISC architecture
Complex Instruction Set Computer
General purpose register Architecture
Variable length complex instructions
Instruction types and addressing modes are provided to
support all types of operations and data transfers
respectively
Instruction decoding is complex
Multi cycle instruction execution
Microprogrammed control unit
680X0 family processors
Example IEEE 754
Convert 6.7523 into 32-bit IEEE 754 format
2.7523=(110.110000001001011011)2
1.10110000001001011011* 2^2
M=10110000001001011011000
E=actual+ bias=2+127=129=(10000001)2
S=0
6.7523= 0 10000001 10110000001001011011000
Example IEEE 754
Convert 1 11011011 0101111100000000001000
Restore Implicite 1. =(1.0101111100000000001000)2
1.0101111100000000001000=1.371095657348632812
5
Exponent= 11011011=219
E=E-bias= 219-127=92
S=1
N= (-1)^S * 2^(E-127) * 1.M
= - (1.3710956573486328125)* 2 ^92