Traffic Light Control

System
Mantık Devreleri
Yrd.Doç. Dr. Mutlu BOZTEPE
Traffic Light Control System
 Chap.6 ve Chap.8’den devam… (inceleyiniz)

Design steps
1. State diagram
2. Sequential circuit design
3. Design State decoder, output
logic and trigger logic
4. Design Timing circuits
5. Implementing
6. Verification
Figure 6--65 Requirements for the traffic light sequence.
Figure 6--66 A minimal system block diagram.
 State Diagram (Chap 6)
VS: Vehicle present on the side street , TL: 25s timer , TS: 4s timer

ANAYOL YEŞİL Tali yolda araç yok ise (VS = ‘0’) hep
bu durumda (state) kal. Araç var ise en
fazla TL (25s) süresi kadar kal.
TS (4s) süresi
sonunda sıradaki
duruma geç Araç varken TL=0 ise (veya 25s
dolduysa) sıradaki duruma geç

Sadece TS (4s) süresi

Sadece TS (4s) süresi
kadar bu durumda kal
kadar bu durumda kal

TL (25s) süresi sonunda veya

TS (4s) süresi
Tali yolda araç yok ise hemen
sonunda sıradaki
bir sonraki duruma geç.
duruma geç

Tali yolda araç olduğu sürece (VS = ‘1’)

en fazla TL (25s) süresi kadar bu
durumda (state) kal TALİ YOL YEŞİL
Figure 6--69 Block diagram of the state decoder, output logic, and trigger logic.
 State State outputs Light outputs Trigger
inputs outputs
S1 S0 SO1’ SO2’ SO3’ SO4’ MR’ MY’ MG’ SR’ SY’ SG’ Long Short
0 0 0 1 1 1 1 1 0 0 1 1 1 0
0 1 1 0 1 1 1 0 1 0 1 1 0 1
1 1 1 1 1 0 0 1 1 1 1 0 1 0
1 0 1 1 0 1 0 1 1 1 0 1 0 1

MR’=m2’.m3’ SR’=m0’.m1’

MY’=m1’ SY’=m2’

MG’=m0’ SG’=m3’

TL’=m1’.m2’
Ts’=m0’.m3’
 S1 S0 MR’

MY’

MG’

SR’

SY’

SG’

MR’=m2’.m3’ SR’=m0’.m1’

MY’=m1’ SY’=m3’

MG’=m0’ SG’=m2’
Figure 8--71 Block diagram of the timing circuits.
 74121 one-shot

TL trigger
TS trigger 10kHz
TS’ TS
TL’ TL CLK
Figure 6--67 System block diagram showing essential elements.
Sequential Logic
 Next state table

Present Stat Next State Input

conditions
Q1 Q0 Q1 Q0
0 0 0 0 TL+VS’
0 0 0 1 T L ’ VS
0 1 0 1 TS
0 1 1 1 TS’
1 1 1 1 TL VS
1 1 1 0 T L ’ + VS ’
1 0 1 0 TS
1 0 0 0 TS’
 Present Stat Next State Input conditions

Q1 Q0 Q1 Q0 Output transitions
0 0 0 0 TL+VS’ QN QN+1 Flip-flop Input
0 0 0 1 TL’ VS 0 0 0
0 1 0 1 TS 0 1 1
0 1 1 1 TS’ 1 0 0
1 1 1 1 TL VS 1 1 1
1 1 1 0 TL’ + VS’
1 0 1 0 TS
1 0 0 0 TS’

Present State Next State Input conditions Flip-flop inputs

Q1 Q0 Q1 Q0 D1 D0
0 0 0 0 TL+VS’ 0 0
0 0 0 1 TL’ VS 0 1
0 1 0 1 TS 0 1
0 1 1 1 TS’ 1 1
1 1 1 1 TL VS 1 1
1 1 1 0 TL’ + VS’ 1 0
1 0 1 0 TS 1 0
1 0 0 0 TS’ 0 0
Present Input Next Flip-flop
State conditions State inputs
Q1 Q0 VS TL TS Q1 Q0 D1 D0
0 0 0 0 x 0 0 0 0
D1=0
0 0 0 1 x 0 0 0 0 State = 0 0
D0=VS TL’
0 0 1 0 x 0 1 0 1
0 0 1 1 x 0 0 0 0
0 1 0 x 0 1 1 1 1
0 1 0 x 1 0 1 0 1 D1=TS’ State = 0 1
0 1 1 x 0 1 1 1 1 D0=1
0 1 1 x 1 0 1 0 1
1 0 0 x 0 0 0 0 0
1 0 0 x 1 1 0 1 0 D1=TS State = 1 0
1 0 1 x 0 0 0 0 0 D0=0
1 0 1 x 1 1 0 1 0
1 1 0 0 x 1 0 1 0
D1=1
1 1 0 1 x 1 0 1 0
State = 1 1
D0=VS TL
1 1 1 0 x 1 0 1 0
1 1 1 1 x 1 1 1 1
 S1 S0

Vehicle
Sensor

TL’ TL TS’ TS
 State decoder,
output logic,
trigger logic

Timing
circuits
To
interface
circuits

Sequential
circuits

Multiplexer Quad AND Flip-flops

gate
Hangisi doğru?
Neden?
Yanlış olanda hata
nedir?
State
inputs in
gray
code

25s one-shot timer 4s one-shot timer 10kHz clock

Hangisi case
doğru? Neden?
Yanlış olanlar da
hata nedir?

State State outputs Trigger outputs

inputs
S S0 SO1 SO2 SO3 SO Lon Short
1 ’ ’ ’ 4’ g
0 0 0 1 1 1 1 0
0 1 1 0 1 1 0 1
1 1 1 1 0 1 1 0
1 0 1 1 1 0 0 1