The Typical Embedded System: B.Thirupathi

The Typical Embedded System
B.THIRUPATHI.
Department of Electronics & Communication Engineering
Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 1

Topics to be covered:
Definition
Embedded systems vs. General Computing Systems
Core of the Embedded System
Memory
Sensors and Actuators
Communication Interface
Embedded Firmware
Other System Components
PCB and Passive

Components
2
Definition
Memory
Embedded Firmware
PCB and Passive Components
3
Definition
Embedded System:
Embedded System is combination of hardware and software, designed
for specific application or domain, whose applications ranges from simple toy
car to complex air traffic control system.

Definition

Memory
Embedded Firmware

General Purpose Computing System Embedded System

A system which is combination of a generic A system which is combination of special
hardware and a general purpose O S for executing a purpose hardware and Embedded O S for executing
variety of applications specific set of applications
 Contains general purpose Operating System (GPOS)  May or may not contain Operating System
Applications are alterable (programmable) by the The firmware of the embedded system is pre-
users.(It is possible for end users to re-install O S , also programmed and it is non-alterable by the end
add/remove user applications) user
Performance is the key deciding factor in selection Application specific requirements(like

of the system. Always ‘Faster is Better’ performance, power requirements, memory usage
etc.) are the key deciding factors.
Less/not at all tailored towards reduced operating Highly tailored to take advantage of the power
power requirements, options for different levels of saving modes supported by all hardware and the
power management. operating system
 Response requirements are not time critical For certain category of Embedded systems like
mission critical systems, the response is time
critical
 Need not be Deterministic in execution behavior Execution behavior is deterministic for certain
types of embedded systems like ‘Hard Real time
systems’

Definition

Memory
Embedded Firmware

Typical Embedded System
FPGA/ASIC/SoC/DSP Embedded
Microprocessor/Microcontroller/COTs Firmware
Memory Communication
Interfaces
I/P Ports Syste O/P Ports

(Sensors) m (Actuators)
Core
Other supporting
ICs & Subsystems
Embedded System
Real
The Typical Embedded System World

1. General Purpose and Domain Specific Processors

a. Microprocessor
b. Microcontroller
c. Digital Signal Processor (DSP)
2. Application Specific Integrated Circuit (ASIC)
3. Programmable Logic Devices (PLDs)
4. Commercial Off the shelf Components (COTS)

Microprocessor Microcontroller
A silicon chip representing a Central Processing A highly integrated chip that contains a CPU,
Unit (CPU) which is capable of performing arithmetic Scratchpad RAM, Special and general purpose
as well as logical operations according to a predefined register arrays, on chip ROM / Flash memory for
set of instructions program storage, timer and interrupt control unit
and dedicated IO ports
It is dependent unit. It requires the combination of It is self contained unit and it doesn't require
other chips like timers. Program and data memory external interrupt control unit, timers, UART etc,
chips, interrupt controller etc. for functioning for functioning
Most of the time general purpose in design and  Mostly application oriented and domain specific
operation
Doesn’t contain built in I/O port. I/O port Most of the processors contain multiple built in
functionally needs to be implemented with the help I/O ports which can be operated as a single
of external programmable peripheral interface chips 8/16/32 bit port or individual port pin.
like 8255
Targeted for high end market where performance is Targeted for embedded market where
important performance is not so critical.(at present, it is
invalid)
Limited power saving options compared to  Includes lot of power saving features
microcontroller

Digital Signal Processor
Are powerful special purpose 8/16/32 bit microprocessor designed specifically to meet the
computational demands and power constraints of audio, video and communication applications.
 2 to 3 times faster than General purpose Processors (architectural difference between the two)
 In general DSP can be viewed as a microchip designed for performing high speed computational
operations for addition, subtraction multiplication and division.
 A typical DSP incorporates the following key units:
Program Memory: for storing program required by DSP to process data

Data Memory : working memory for storing temporary variables and data/signal to be processed
Computational Engine : performs signal processing in accordance with stored program.

Computational engine incorporates many specialized arithmetic units and each of them operates
simultaneously to increase the execution speed and also shifters
I/O unit: acts as an interface between the outside world and DSP. It is responsible for capturing signals
to be processed and delivering the processed signals.
Audio, Video signal processing, telecommunication and multimedia applications are typical examples.
Involves Real time operations like Su m of Products(SoP), Convolution, FFT, DFT etc.

RISC CISC
Reduced Instruction S e t Computer Complex Instruction S e t Computer
 Lesser number of Instructions  Greater number of instructions
Instruction Pipelining and increased execution  Generally no instruction pipelining feature

speed
Orthogonal Instruction set.(Allows each instruction Non-Orthogonal Instruction set.(All instructions
to operate on any register and use any addressing are not allowed to operate on any register and use
mode) any addressing mode. It is instruction specific)
 A large number of Registers are available.  Limited number of general purpose registers.
Programmer needs to write more code to execute a Instructions are like macros in C language. A
task since the instructions are simpler ones programmer can achieve desired functionality
with a single instruction which in turn provides
the effect of using more number of instructions
in R I S C
 Single fixed length instructions  Variable length instructions

 Less silicon usage and pin count More silicon usage since more additional decoder
logic is required to implement the complex
instruction decoding
 With Harvard Architecture  Can be Harvard or Von-Neumann Architecture

Harvard Architecture Von-Neumann Architecture
I/O CPU Memory

Program Data
CPU Memory
Memory
Single shared
 Separate buses for instruction and Data fetching Single shared bus for instruction and data
fetching
Easier to pipelining, so high performance can be  Low performance compared to Harvard.

achieved
 Comparatively high cost  Cheaper
 No memory alignment problem  Allows self modifying codes
 Since data memory and program memory are Since data memory and program memory are
stored physically in different locations, no stored physically in same location there is
chances for accidental corruption of program chance for accidental corruption of program
memory memory

Big Endian vs. Little Endian Processors/Controllers
Endianness specifies the order in which the data is stored in memory by the processor operations in a
multi byte system.
 Let us consider a 4 bytes long integer Byte 0, Byte 1, Byte 2 and Byte 3
Base Address + 0 BYTE 0 0x2000 (Base Address) Base Address + 0 BYTE 3 0x2000 (Base Address)
Base Address + 1
BYTE 1 0x2001 (Base Address + 1) Base Address + 1
BYTE 2 0x2001 (Base Address + 1)
Base Address + 2 BYTE 2 0x2002 (Base Address + 2) Base Address + 2 BYTE 1 0x2002 (Base Address + 2)
Base Address + 3
BYTE 3 0x2003 (Base Address + 3) Base Address + 3
BYTE 0 0x2003 (Base Address + 3)
Lower-order byte of data is stored in memory at Lower-order byte of data is stored in memory at
lower address higher address
Higher-order byte of data is stored in memory at Higher-order byte of data is stored in memory at
higher address lower address
Little Endian Operation Big Endian Operation

Assignment Q1: Consider Data 0xff001234, store this data in memory with starting address from 0x1d04,
Assume each memory location can accommodate 1 byte of data. Show diagrammatically Big Endian
Storage and Little Endian Storage.

Load Store Operation a n d Instruction Pipelining
1. load R1,x
2. load R2,y
3. add R3, R1, R2
R1 R2 R3 4. store R3,z
00 x
7F ALU
23 y
z
The concept of Load and Store Architecture

Instruction Pipelining
1 2 3 4 5
Fetch Execute
Fetch Execute
Fetch Execute
Fetch Execute
1 2 3 4 5 6 7 8
Fetch Execute Fetch Execute Fetch Execute Fetch Execute

Application Sp e c ifi c Integrated Circuit ( ASIC)
 AS I C is a micro chip designed to perform a specific or unique application
Integrated several functions into a single chip and there by reducing system development cost. Most
of the ASICs are proprietary products,
As a single chip AS IC consumes a very small area in total system and thereby help to design smaller
systems with high capabilities/functionalities.
Can be pre-fabricated for a special application or it can be custom fabricated by using components
from a re-usable “building blocks” library of components for a particular customer application.
 AS I C based systems are profitable only for large volume commercial products.
Production of ASI C requires a non-refundable initial investment for the process technology and
configuration expenses- N R E (Non Recurring Engineering Charges), it is one time investment
If N RE is borne by Third Party and AS IC is made openly available in the market, ASI C is
referred as Application Specific Standard Product (ASSP)
Disadvantages: Since ASICs are proprietary products, the developers of such chips may
not be interested in revealing the internal details of it, hence it is very difficult to point out
example of it.
It creates legal disputes if an illustration of such an AS IC product is given without prior
The permission from manufacturers

Typical Embedded System of AS IC

Programmable Logic Devices( PLDs)
Logic devices provides specific functions, including device-to-device interfacing, data communication,
signal processing, data display, timing and control operation.
 logic devices can be classified into 2 broad categories:
F i xe d L o g i c D ev i c e s --- Perform one/set of functions once manufactured

Programmable Logic Devices --- offers customers a wide range of logic capacity, features, speed and
voltage characteristics
---can be reconfigured to perform no. of functions at anytime
 With PLDs, designers use inexpensive software tools to quickly develop, simulate and test their
designs.
Design can be quickly programmed into a device and immediately tested in a live circuit.
There are no N RE costs and the final design is completed much faster than that of a custom, fixed
logic devices.
Key Benefit: During design phase customers can change the circuitry as often as they want until design
operates to their satisfaction.
PLD are based on re-writable memory technology. Once design is final, customers can go into
immediate production by simply programming as many PLDs as they need with final S/W design file.

Programmable Logic Devices( PLDs) contd.
 PLDs can be classified into 2 broad categories:
CPLDs --- Complex PLDs
FPGAs --- Field Programmable Gate Arrays
 FPGAs offer highest amount of logic density,

most features, highest performance
 Largest FPGA now available is Xilinx Vertex
with 8 million system gates
Advanced FPGAs also provides hardwired processors, substantial amount of memory, clock
management systems and support latest technologies.
Are used in wide variety of applications ranging from data processing and storage, instrumentation,
telecommunication and Digital Signal Processing

 CPLDs offer much smaller amount of logic (10,000 Gates).
 But offer very predictable timing characteristics and are ideal for critical control applications
Also requires low amount of power and very inexpensive, hence ideal for cost sensitive, battery
operated, portable applications such as mobiles and digital handheld assistances

Programmable Logic Devices( PLDs) contd.
 Advantages of PLDs:
• Offers more flexibility during design phase.
• Doesn’t require long lead time for prototyping
• Do not require large N R E cost
• PLD offers customers to order just no. of parts they need, when they need them, allowing them to
control inventory. Fixed PLDs customers end up either with excess inventory or caught short of
parts which delays production.
• Can be programmed even after it is shipped to customers- up gradation by uploading program

files to internet
Few years ago largest FPGA measured is 10s thousands of system gates and operated at 40Mhz.
Currently million of gates with integrated functionality like Processors and memory, operating at 300MHz
Assignment Q2: Which is the largest FPGA currently available in market and
what is its operating frequency?

Commercial Off the S h e l f Components ( COTS)
Designed in such a way to provide easy integration and inter-operability with existing system
components.
 May be developed around a general purpose/ domain specific/ ASIC/ PLD
Typical examples - remote controlled toy car unit including the R F circuitry part, high performance
and high frequency microwave electronics, high bandwidth ADC, devices and components for operation
at very high temperature, electro-optic IR imaging arrays, UV/IR detectors etc.
Readily available in market, cheap and a developer can cut down his/her development time to a great
extent, reducing time to market.
TCP/IP plug in module available from various manufacturers like WIZnet, Freescale, Dynalog etc. are
very good examples of C OT S
 You have to identify C OT S for your system and give plug-in option on your board
Though multiple vendors supply C OT S for same application there is no operational and manufacturing
standards
 C OT S manufactured by a vendor need not be having hardware plug-in and firmware compatibility with
one manufactured by a second vendor.

This restricts end-users to stick to a particular vendor for a particular C OT S
C OT S Manufacturers may withdraw the product/discontinue at any time if a rapid change in
technology occurs.

Definition
Memory
Embedded Firmware
PCB and Passive

Components

Memory
On-Chip Memory and Off-chip Memory Volatile Memory and Non Volatile Memory
Serial Memory and Parallel Memory RO M and RAM
Program Storage Memory (ROM):
Code
FLASH Memory NVRAM
(ROM)
PROM MASK ROM

EPROM EEPROM
(OTP) (MROM)

Memory
Masked ROM  One Time Programmable
 Programmed by masking and metallization process at the time of production
itself based on input given by user
 Low cost , good for storing Firmware for low cost embedded devices.
Once the design is proven and tested, the binary data corresponding to it can
be given to M RO M Fabricator
Disadvantage: disability to modify Firmware
PROM  One Time Programmable
 Unlike M RO M it is not preprogrammed by manufacturer

 The end user programs these devices.
has nichrome/polysilicon arranged as matrix. These wires can be used as
fuses.
it is programmed by selectively burning these fuses according to bit pattern
to be stored
fuses not blown represents ‘1’ and those blown are logic ‘0’. Default state is
logic ‘1’
used for commercial production of embedded systems whose prototype is
proven and code is finalized.
low cost is advantage but cannot be reprogrammed

Memory
E PROM  Provides the flexibility to reprogram the same chip
 Stores the bit information by charging the F E T gate
 Contains quartz crystal window for erasing the stored information.
if this window is exposed to UV rays for a fixed duration, the entire memory will be erased
for erasing process, it needs to be taken out of circuit board and put in a UV eraser device
for 20-30 mins, which is tedious and time consuming
EE P ROM  Information contained in E E P RO M can be altered by electrical signals at register/byte level

 Ca n be erased and reprogrammed in-circuit
consists of a ‘chip erase mode’, in this mode they can be erased in ms.
provides flexibility for system design
only limitation is capacity compare to standard RO M
F L ASH  Latest RO M
 Variation of EEP RO M
combines flexibility of E E P RO M + High capacity of Standard RO M .
organized as sectors(blocks) or pages.
stores information in an array of floating gate M O S F E T transistors.
memory can be erased at sector/page level without erasing other sectors
each page/sector must be erased before reprogramming, typical erase cycles is 1000 cycles

Memory
NVRAM  Memory with battery back up
 Consists of S RA M memory with minute battery
 Memory and battery are packed in a single package
life span is expected to be around 10 years
Read/ Write Memory or Random Access Memory (RAM):
Data
Memory
(RAM)
SRAM DRAM NVRAM

Memory
S RA M  Data is stored in the form of voltage
 Made up of flip-flops
 Fastest form of RAM
typically realized using 6 M O S F E T S
4 for building flip-flops; 2 for controlling access
in simple form SRAM is a 2 Cross-coupled inverters with read/write control through transistor.
access to memory cell is controlled by word line
for writing, desired value is applied to bit line controller. i.e. for 1, B=1 and B’=0
for 0, B=0 and B’=1
for reading, both the bit lines are asserted/set as 1 and word line is set to 1

Memory
DRAM  Dynamic RAM
 Data is stored in the form of charge
 Made up of a M O S transistor gate
high density and low cost
Charge gets leaked away hence periodic refresh is done
DRAM Controller refreshes DRAM after certain msecs.
M OSFET acts as gate for incoming and outgoing data
capacitor acts as bit storage unit
S RA M DRAM
made up of 6 C M O S transistors (MOSFETs) made up of a M O S F E T and capacitor
doesn’t require refresh periodic refresh is necessary
low capacity (less dense) high capacity
expensive less expensive
fast in operation, 10 ns access time slow in operation due to

refreshment 60 ns access time
Write is faster than read

Memory
Memory Shadowing
Advantage Limitation
 RO M access speed is very slow compared to ROM Non Volatile Slower
RAM
 RAM is 3 times faster than RO M

RAM Faster Volatile
 Shadowing technique is adapted to solve

execution speed problem
Basic I/P O/P configuration ROM or BIOS stores hardware configuration information
like address of various ports.
Now manufactures include RAM behind BIOS at its same address, as a shadow BIOS
First step during Boot up is copying of BIOS to shadowed RAM and write protecting
this RAM and disabling BIOS
RAM is volatile but R O M is perm anent , therefore high system performance is

achieved by accessing RAM instead of RO M

Memory
Memory Selection for Embedded System
Code Memory (ROM)
Application Specific
 Data Memory (RAM)
if made up of S o c / M C , on-chip memory may be enough, if not must be interfaced with external/off-
chip memory
ROM + RAM to execute program code, for RTO S based embedded system extra RAM is required for
Memory Shadowing
Memory Chip Size available in standard size like 512/1024 bytes (1Kb, 2Kb, 4Kb, 8Kb, 1Gb, 2Gb,
4Gb, 8Gb)
suppose memory required is 740 bytes, 1Kb chip can be selected
word siz e no. of bits that can be accessed simultaneously, word size <==> bus size
currently FLASH memory is used

FLASH memory NAND FLASH memory High density, low cost , DRAM is used
NOR FLASH memory low density, slightly expensive but supports XIP
(execute in place)

Definition
Memory

Embedded Firmware
PCB and Passive

Components
 Sensor is a transducer that converts energy from one form to another for any
measurement and control purpose
 Actuator is a transducer device (mechanical/electrical) which converts signals

to corresponding physical actions
 Input Output Subsystem facilitates interaction between Embedded

System and external world
Light Emitting Diode (LED)
o/p device for visual indication of signal status like

device ON, Battery Low, charging state
its an p-n junction diode,

anode +ve terminal of Power supply
cathode -ve terminal of Power supply
current conducted by LE D is limited, therefore to limit current through LE D within

maximum value, resistor is connected in series
LE D and MP/ MC is interfaced in 2 ways
 Anode is connected to port pi of MP /M C and cathode is connected to ground
brightness depends on current sourced by port pin,

may be not of required level
 Cathode is connected to port pin and anode is connected

to power supply
brightness is of required level
Seven Segment Display

o/p device for displaying alpha-numeric characters
popular choice for low cost Embedded applications

like public telephone call monitoring device, point of
sale terminal etc.
8 LE D segments are arranged in special form

7 are used for displaying Alpha-numeric characters
named as A to G
1 LE D is used for displaying decimal
point in decimal numbers and named as DP
When interfaced with M P/M C 8 LE Ds are connected such that A is connected to LSB
port pin and DP is connected to M S B port pin
 C a n be interfaced with M P/ M C using any of 2 configurations:
Common Anode
 Co mmon Cathode
 In Common anode , anodes of all the LEDs

are connected commonly and connected to
5V power supply whereas cathode of each LE D
is connected to Port Pins
 In Common cathode, cathodes of all
the
LEDs are connected commonly and connected
to ground whereas anode of each LE D is
connected to Port Pins
 The current through each LE D must be

limited below maximum value. It is typically
20mA by
The Typical connecting
Embedded current limiting resistor to
System
anode/cathode
Optocoupler:
to isolate 2 parts of circuit
LED + photo transistor in single package
can be used for suppressing data interference in data

communication, circuit isolation, high voltage
separation, signal intensification
optocoupler can be used at input or output of a

circuit
optocoupler is available as IC M CT2 M

Stepper motor:
electro-mechanical device that generates discrete displacement in response to D C
electrical signals
widely used in industrial embedded applications, consumer electronic products and
robotic control systems
based on coil winding arrangements, a 2 phase stepper motor is classified into 2
types: Unipolar Stepper Motor
 Bipolar Stepper Motor
Unipolar Stepper Motor
2 windings per phase
direction of rotation is controlled by changing direction of current flow

current in these 2 coils flow in opposite direction wrt. to each other
change of direction implies changing/switching \terminals to which

coils are connected
coils are represented as A, B, C and D. A & C carry current in opposite
direction for phase 1, similarly B & D carry current in opposite direction
for phase 2
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Bipolar Stepper Motor
single winding per phase
direction of motor rotation is dynamically reversed
complex circuit is necessary for current reversal
I m p l e m e n t a t i o n : by changing sequence of activation of stator windings different stepping

modes can be implemented
Step A B C D Full Step:

Both phases are energized simultaneously
1 H H L L
2 L H H L
3 L L H H
4 H L L H

Step A B C D  Wave Step:

Only one phase will be active at a time
1 H L L L
2 L H L L Step A B C D
1 H H L L
3 L L H L
2 H L L L
4 L L L H
3 L H H L
4 L H L L
5 L L H H
6 L L H L
Half Step:
7 H L L H
Combination of full step and wave step
8 L L L H

2 phase unipolar stepper motors are popular choice
current requirement for stepper motor is little high, hence port pin of MP / MC may not
be able to drive stepper motor, normally requires 5v-24v supply voltage
therefore special circuits are required to interface stepper motor to MP/MC=> COTS->
ULN2803
39
Relay:
electro-mechanical device
dynamic path selector for signals and power
made up of 2 components:
Relay coil made up of insulated wire wound over a metal core
Metal armature with one or more contacts
works on electromagnetic principle
when voltage is applied to relay coil, current flows through the coil which generates
magnetic field, this magnetic field attracts/reflects armature and moves the contact
point
2 configurations single core and single throw only 1 path for information flow
single core and double throw 2 paths for information flow and selected by
energizing and de-energizing the coil
single core and single throw

normally open
normally closed
40
normally controlled using a relay driver circuit connected to the port pins of MP /M C
relay driver circuit is built using transistor
free wheeling diode is for protecting relay and transistor
special relays  Reeds are available for embedded applications for switching low
voltage D C signals
41
Piezo-buzzer:
piezo-electric device for generation of audio indication in embedded applications
piezo electric diaphragm produces audible sound in response to applied voltage

2 configurations:
Self Driving generates sound at a predefined tone

 External Driving supports generation of different tones.
Tone can be varied by applying variable pulse train
can be directly interfaced or through a transistor based driver circuit
Push Button Switch:

input device
2 configurations:
Push to make
 Push to break
42
Push t o m a ke switch is normally open
makes contact when pushed or pressed
remains in the closed state unless it is released
when released breaks connection
 Push to break switch is normally closed

breaks the contact when pushed or pressed
remains in the open state unless it is released
when released circuit connection is made back
used for generating a momentary pulse i.e.

pulse generator, reset and start pulse
high pulse/ low pulse depends on how it is

interfaced with MP /M C
43
Keyboard:
input device
if keys required is very less, push buttons can be directly interfaced to port pins
if large number of keys are required for user inputs then it is not possible to interface
all the keys, also it will be wastage of port pins
best solution for such case is Matrix keypad

it generally reduces to number of interface
connections. For example
If 16 keys required, it requires 16 port pins
Instead if 4x4 matrix keypad is used only
4+4 =8 port pins are required i.e. 50%
reduced
In matrix keyboard, keys are arranged in

matrix fashion
44
Detecting a Key pressed:
Scanning Technique
each row of matrix is pulled low and column is read
after reading status of each column corresponding o a row, that row is pulled high and next row is
pulled low and process is repeated unless all the rows are checked
when row is pulled low and a key connected to that is pressed then
when status of column is read, it gives logic 0
Disadvantage: keys are mechanical therefore suffer from
Sw i t ch Debouncing  multiple key pressed effect for

single key pressed
H/w key Debouncing circuits:

additional H/W is required
S/W key Debouncing technique:
once key pressed is detected, it is read again after
certain debouncing delay, if key pressed is genuine,
the state remain same on second read also.
pull up resistors are connected to column lines to limit the

current that flows through rows when key is pressed

Programmable Peripheral Interface:
used for enhancing I/O capabilities of MP /M C
MP/MC provides limited number of I/O port pins, in some cases there may be need for
more number of I/O pins than that is supported by MP / MC
 8255A is popular PPI device it supports 2 4 I / O pins
three 8 bits parallel ports  port A, port B and port C

or two 8 bits parallel ports  port A and port B
Port C as 8 individual port pins
or
Two 4-bit parallel
ports Port C upper and
Port C Lower
Control Register of 8255A
Assignment Q3: Explain the bit fields of

Control Register of 8255A PPI Device

Definition
Memory
Embedded Firmware
PCB and Passive

Components

essential for communicating with various subsystems of the embedded system and
also with other systems.
2 prospective:
Device/Board level on-board Communication Interfaces
 Product level External Communication Interfaces
On-board C om m unication In terfaces => c omm unication links which interconnect

different subsystems/components with in a Embedded System
E xamples: I2C , Serial Peripheral Interface, UART , 1- interface, Parallel

wire Interface
External Communication Interfaces => communication links which facilitates

interaction and data transfers between different devces/systems in a distributed
network wired or wireless
Examples: R S 232C & R S 485, US B, I E E E 1394, IrDA, Bluetooth, Wi-Fi, Zig

bee, G P RS
48
On-board Communication Interfaces
Inter Integrated Circuit (I2C) Bus:
synchronous, bi-directional, half duplex & 2 wire serial interface bus

concept of I2C bus Philips Semiconductor in early 1980s
original intention provide easy communication interface between MP /MC and
other peripheral chips of TV
2 wires:
Serial Clock (SCL)
 Serial Data (SDA)
SCL  for generation of clock
pulse for synchronization
S DA  for transmitting serial data between the

devices
Shared bus system  multiple devices

connected to a single bus
Device  Master/Slave
49
Master  controls communication by initiating/terminating data transfer, it sends
data, generates synchronous clock pulse
Slave  waits for the commands from Master and responds on receiving the commands
Master/Slave  Transmitter/receiver, regardless of Transmitter/receiver Master

generates the clock pulse
I2C  Supports multiple master devices
connection of master and slave on I2C bus is as

shown in figure
for proper operation of bus both the lines are

pulled to high voltage  5V for TTL logic and 3V for
C M O S Family devices, through pull up resistors of
2.2 KΩ
therefore with pull-up resistors, the output lines

of bus in ‘idle state’ is High
50
Sequence of operations for communicating between Master & Slave:
 Master device pulls the clock line (SCL) HI G H

 Master device pulls the data line (SDA) LOW
Therefore: S C L  HIGH
 START Condition for data transfer
SDA  LOW
master device sends address (7-10 bits) of slave

device with which it wants to communicate over S DA
master device sends read/write bit
i.e. if Bit Value = 1, R EAD operation

Bit Value = 0, WRITE operation
master device waits for the acknowledge bit from

the slave device, whose address is sent along along
with read/write operation command
salve compares received address with its address
51
 slave device with address requested by the master responds by sending
acknowledgement (Bit value 1) over S DA line
upon receiving acknowledgement bit master device sends 8 bits data to slave device
over S DA line  if requested operation is ‘WRITE to device’ else
if requested operation is ‘READ from device’ then slave device sends data to master
over S DA line.
master device awaits for the acknowledge bit

from the slave device upon byte transfer if WRITE
operation else sends a acknowledgement bit to
salve for RE AD operation
master device terminates the transfer by pulling

SDA line HIGH when S C L is HIG H
Therefore: S C L  HIG H
 STOP Condition for data transfer
SDA  HIG H
52
 I2C supports different data rates:
Standard Mode 100 kbps
Fast Mode 400 kbps
High Speed Mode  3 . 4 Mbps
Serial Peripheral Interface (SPI) Bus:
synchronous, bi-directional, full duplex & 4 wired serial interface bus

concept was first developed by Motorola
supports single master and multiple slave
also supports more than one master  only one master is active at a time
4 wires:
Master Out Slave In (MOSI)Slave In/Slave Data In(SI/SDI)

 Master In Slave Out (MISO)Slave Out/Slave Data Out(SO/SDO)
Serial Clock (SCL)  carry clock signal
 Slave Select (SS)  active low
53
Master generates Clock Pulses
selects the slave device by asserting the slave selecting signal low
Data exchange through SPI fully configurable
Serial Peripheral Control Register

 stores all configuration parameters
like selection of master/slave for data

transfer, selection of baud rate for
communication, clock signal control,
whether MS B/ LSB should be sent first
SPI works on Principle of Shift

register
Master Slave
1 0 0 1 0 1 1 0 MOSI 1 0 0 1 0 1 1 0
0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1
MISO
therefore Shift registers of Master & Slave form a
Circular buffer
54
master and slave devices contains a special shift registers for data transfer. Size of
the shift register is device dependent, normally it is multiple of 8
suitable for applications which supports data transfer in streams
only disadvantage is that it doesn’t support acknowledgement mechanism
Universal Asynchronous Receiver Transmitter (UART) Interface:
asynchronous type of data transmission

no need of clock pulse
transmission takes place based on predefined agreement between Transmitter
& Receiver
serial communication settings: Baud rate, number of start bits, parity, number
of
bits per byte and flow control, should be identical between transmitter & receiver
special bits in data stream indicates start and stop of data transmission
while sending a data byte, a start bits are added first and stop bits are added the
end
parity bit
of a byte Stop LSB
of data bit follow
MSB start bit. LSB Start bit
55
 Start bits inform receiver that a data byte is about to arrive
 If baud rate is x bps, time slot for each bit is 1/x seconds. For example if baudrate is
5 then 1/5 seconds.
1/5 (1000) ms = 200ms
 If parity is enabled then UART of transmitting device adds parity bit
1  number of 1’s is odd or vice-versa

0  number of 1’s is even
 UART on receiver device calculates the parity of bits received and compares it with
parity bit for error checking
 UART on receiver device discards the ‘Start’, ’Stop’ and ‘Parity’ bits from received
bit stream and converts the received signal bits into words
 For proper communication, transmitter

line of sending device must be connected to
receiver line of receiving device.
56
 UART chips are available from different semiconductor manufacturers but National
Semiconductor’s 8250 UART is considered to be standard
 Now a days most of the MP / MC are available with integrated UART functionality and
they provide built-in instructions to support serial data transmission and reception
1 wire Interface:
asynchronous, half duplex

developed by Maxim Dallas Semiconductors
also known as Dallas 1 wire protocol
made up of only single signal line called as
DQ for communication, follows master slave
communication model
supports single master and one or more slave
devices
57
 Every 1-wire device contains a globally unique 64 bits identification number. This
UIN can be used for addressing individual devices on bus.
 the identifier has 3 parts 8 bits family code T T L/CM OS

48 bits serial number
8 bits C R C generated from first
56 bits
 Sequence of operation:
 Master device sends a ‘Reset’ pulse over 1-wire
 Slave device(s) present on bus

responds with a ‘Presence’ pulse
Master device sends a RO M command 

64 bits address of device
th is addresses the slave device
with which it want to communicate
Master sends read/write function

com m and to read/write into
memory of slave device internal
Master initiates read/write from the

device or into the device
58
 Communication over 1-wire bus is divided into time slots of 60µsecs
 For starting the communication, master asserts the Reset pulse by pulling 1-wire bus
Low for at least 8 time slots
 If slave devices are present on bus and is ready for communication, should respond
with ‘Presence’ pulse within 60µsecs of reset pulse
 For writing a bit value 1, master pulls the bus LOW for 1-15µsecs and releases for the
rest of the time slots.
 A bit value is written by master pulling the

bus LOW for minimum 1 time slot and
maximum 2 time slots.
To read a bit from slave master pulls the bus

LOW for 1 to 15µsecs. If slave wants to send bit
value ‘1’, it simply releases bus for rest of the
time slot
If slave wants to send bit value’0’, it pulls the
bus low for rest of the time slot
59
Parallel Interface:
for communicating with peripheral devices which are memory mapped to host system
the host MP/ MC of Embedded system contains a parallel bus & devices can be
directly connected to this bus
c om munication through parallel bus is c ontrolled by C ontrol Interface
Signal between device and host.
 Control Signals:
Read/write signal controls direction of data transfer
Device Select signal device activates only when this signal is asserted
address decoder is used for generating chip

select signal for selecting device
if address selected by processor is with in

range assigned for devices, the decoder
activates the chip select line and thereby the
device becomes active
60
the processor can then read/write from/to the device by asserting RD/WR’ control
lines
parallel communication is host initiated. If the device wants to communicate, it

can inform by generating a interrupt.
bus width supported by device must be same as that of host processor (usually 4
bits, 8, 16,32 or 64 bits)
offers the highest speed for data transfer
61
External Communication Interfaces
R S 232C & R S 485:
R S 232C  Recom m ended Stan dard number 232 from Electronic

revision C Industries Association
full duplex, wired, asynchronous serial communication

was developed by EIA in 1960s
Extends UART communication for external data communication
follows EIA standard for bit transmission

according to EIA logic 0 = +3v to +25v, Space
 logic 1 = -3v to -25v, Mark
supports 2 different types of connectors
DB-9  9 pins connector
DB-25  25 pins connector
RS 232  point to point
communication
Devices involved  Data Terminal
Equipment (DTE)
 Data Communication
Equipment (DCE)
62
No control signals are required
only TXD and R X D lines and Gnd line are required
the R X D pin of D C E must be connected to T XD pin of DTE and vice versa for
proper communication
Request to send (RTS) and Clear to send (CTS) coordinate the communication
between DTE and D C E
DTE ----------------------------- D C E
 DTE activates RTS line

 D C E activates C T S line
 D C E sends D C D (Data carrier Detect) to indicate good signal is received
 DTE -----------------------------DCE
 DTE activates Data Terminal Ready (DTR) if ready to accept
 D C E activates Data S et Ready (DSR) when it wants to send data
As per EIA R S 232 supports Baud rate upto 20Kbps
Commonly used Baud rates are  300bps, 1200 bps, 2400 bps, 9600 bps,
11.52 kbps, 19.2 kbps
63
distance supported is 50 feet with full speed
Embedded systems contain UART for serial communication. A level transistor I C

from Maxim Dallas semiconductor is used for converting the signal lines from UART
to R S 232 signal lines for external communication
RS 232 supports only point to point communication and not suited for multiple
drop communication
more susceptible to noise, reduced operating distance
 RS 422 supports data rates upto 100 Kbps and distance of 400 ft
Same R S 232 is used at device end R S 232 – RS422 converter is plugged-in and
at the receiver end R S 422 to R S 232 converter is used
RS 422 supports multi drop communication with one transmitter and upto 10
receivers
 RS 485 is enhanced version of R S 422 and it supports upto 32 transmitters and

32 receivers
64
Universal Serial Bus (USB):
 Wired high speed serial bus
first version USB 1.0 was released in 1995 and created by USB core group
members including  Intel, Microsoft, IBM, Compaq, Digital & Northern Telecom
follows star topology with USB host at center and one or more USB peripheral
devices/USB hosts connected to it.
USB transmits data in packet form and each packet

has standard format
USB communication is initiated by host
USB host is made up of USB controller,

which is responsible for controlling the
data c om m unication,
establishing connectivity with USB slave
devices, Packetizing and formatting the
data
65
 2 different standards for USB host control interface:
Open Host Control Interface (OHCI)
Universal Host Control Interface (UHCI)
 Physical connection between USB peripheral device and master device is

established using a USB cable. This cable supports communication distance upto 5
meters.
 USB standards use 2 types of connectors (at the end of USB cable):
‘Type A’  for upstream connection (connection with host)
‘Type B’  for downstream connection (connection with slave)
 Both Type A and Type B have 4 pins:

V bus  Carrier power (5V)
D- differential data carrier line
D+ differential data carrier line

GND  Ground Signal line
66
 Uses differential signals for data transfer. This increases the immunity of signal
 USB interface has ability to supply power to connecting devices. 2 pins (power &
GND) is dedicated for carrying power. Can carry upto 500mA at 5V enough for low
power devices.
 USB devices must have:

 Product ID (PID)
 Vendor ID(VID)
 USB supports 4 different types of data transfer:

1. Control  query, configure, issue commands to USB Drivers
2. Bulk  Sending block of data, supports error checking & correction(data to printer)
3. Isoc h ron ou s  R eal tim e data c om m unication, data is transmitted as

streams (audio devices, medical equipments)
4. Interrupt  Small amount of data, uses polling  checks whether USB device has
any data to send
67
 USB supports 4 different rates:
Low speed  5 Mbps  USB 1.0
full speed  12 Mbps  USB 1.0 High
speed  480 Mbps  USB 2.0

Super speed  4.8 Gbps  USB 3.0
I E E E 1394 (Firewire):
 Wired, synchronous, high speed

serial communication bus
also known as High Performance
Serial Bus
implementation from different manufacturers with different
name Apple I n c .  Firewire
S ony Corp.  I L I N K
Texas I n s t r u m e n t s Lynx
supports peer to peer connection and point to multi point communication allowing
63 devices to be connected on bus in a tree topology
The it’s a wired

Typical technology
Embedded Systemand it can support a cable length of upto 15 feet for
interconnection
68
 As evolved from I E E E 1394 1995 - I E E E 1394 2008
 Supports a data rate of 400 to 3200 Mbps
 Uses differential data transfer & interface cable supports 3 types of connectors
namely:  4 pins connector
 6 pin connector (alpha connector)
 9 pin connector (beta connector)
 6 pin & 9 pin connectors also carries power ranging from 24 to 30V
Pin name 4 6 9
 There are 2 differential lines A & B normally pin pin pin
differential lines of A are connected to B and vice versa. Power 1 8
 Popular communication interface for connecting Signal ground 2 6
embedded devices like camera, scanners, camcorders to TPB- 1 3 1
desktop for data transfer and storage TPB+ 2 4 2

TPA- 3 5 3
 Data rate supported by 1394 is for higher than the one
TPA+ 4 6 4
supported by USB TPA(s) 5
 1394 implementation is mu ch costlier than USB TPB(s) 9
implementation NC 7
69
Infrared(IrDA):
 serial, half duplex, line of sight based wireless technology
remote control of TV, VC D etc. works on infrared technology
uses infrared waves of electromagnetic spectrum for transmitting the data

supports point to point and point to multi point communication provided all devices
involved are within line of sight.
typical range lies in 10cm to 1m, can be increased by increasing transmitting power
of IR device.
supports data rates ranging from 9600bps to 16Mbps
 Depending upon speed of data transmission IR is classified into

Serial IR (SIR)  9600bps to 115.2 Kbps
Medium IR (MIR)  0.576 Mbps to 1.152 Mbps
Fast (FIR)  Upto 4 Mbps
Very Fast IR (VFIR)  Upto 16Mbps
Ultra Fast IR (UFIR)  targeting 100Mbps
(Developing Phase)
70
 IrDA communication involves a transmitter unit for transmitting the data
over IR and Receiver for receiving data
Infrared LE D is the IR source for transmitter and at the receiving end a photo
diode acts as receiver
usually m ost of Ir-devices con tains both transm itter and receiver called as
transreceiver for bidirectional communication
some of the devices have either TxD or RxD.
Example: TV remote control system

TV Remote  TxD
TV  RxD
Infrared Data Association (IrDA) is regulatory body responsible for defining and
licensing the specification for IR data.
IrDA communication has 2 parts

A physical link part physical transfer of data
A protocol part  Defining rules for communication
71
C ontrol protocol contains implementation for Physical layer (PHY),
Media Access Control (MAC) and Logical Link Control (LLC)
 physical layer defines physical characteristics like range, data rates, power etc.
IrDA is popular for file exchange and data transfer in low cost devices.
IrDA was widely used before the discovery of Bluetooth
Bluetooth:
 Low cost, low power, short range, wireless technology for data and voice communication
was first proposed by Ericsson in 1994
operates at 2.4 G Hz of Radio Frequency spectrum and uses Frequency Hopping
Spread Spectrum (FHSS) technique for communication
supports data rate of upto 1Mbps and range of 30 feet

Similar to IrDA, Bluetooth has 2 essential parts
A physical link part physical transmission of data between the device using wireless
principles of R F waves
A protocol part  Defining rules for communication
72
Each bluetooth device will have a 48 bit Unique Identification Number(UIN).
Bluetooth follows packet based data transfer
Bluetooth supports point to point and point to multi point communication.

point to point master slave approach
point to multi point1 master more slaves Piconet
 A Piconet supports maximum of 7

slaves
Bluetooth is favorite choice for short range communication in handheld devices.

Very popular for cell phones for transferring ringtones, music files, pictures, media files
etc.
Generic Access Profile (GAP) defines the requirement for detecting a Bluetooth
device and establishing a connection with it
Serial Port Profile (SPP) defines serial data communication
File Transfer Profile (FTP) defines file transfer between devices

Human Interface Devices (HID) for supporting human interface devices like keypad,
mouse etc.
Bluetooth Special Interest Group (SIG) defines specification and license the
specification.
73
Wi-Fi (Wireless Fidelity):
popular for networked communication of devices
follows I E E E 802.11 standard
essential to have device identities in a multi point communication to address

specific device for communication
In Internet Protocol communication each device is identified by an IP

address
unique to each device on a network
Wi-Fi communication requires an intermediate agents called Wi-Fi router.

Access Port(WAP) • Assigning IP address to a device on network
Wireless
• Routing data packets to intended devices on network
Wi-Fi enabled devices contains a wireless adaptor for transmitting and receiving data
in the form of radio signals through an antenna  H/W part is called as Wi-Fi Radio
For communicating with devices over a Wi-Fi network, Wi-Fi Radio when turned ON,
it searches for the available Wi-Fi network in its vicinity & list out the Service S et
Identifier (SSID) of available networks.
74
If network security is enabled, Password will be required
employs Wired Equivalency Privacy (WEP) and Wireless Protected Access (WPA)
for data security
data rates 1 Mbps to 150 Mbps depending on type of antenna and

location(outdoor/indoor) usage
Operating range is 100 to 300

feet
Zig-Bee:
low power, low cost, wireless network communication protocol

based on I E E E 802.15-2006 standard.
targeted for low power, low data rates and secure applications for wireless Personal
Area Networking (WPAN)
supports mesh-networking containing multiple nodes. Mesh topology makes network
more reliable as it provides multiple paths to get data from one node to another,
operates at 3 frequency ranges  2.4 to 2.484 G Hz

902 to 928 MHz
868.0 to 868.6 MHz
75
operating range is of 100 mts and data rates of 20-250 Kbps
In Zig Bee network each device falls under any one of
following devices:
Zig Bee coordinator/Network Coordinator(ZC)
acts as root of ZigBee network
has capability to store more information about the
network
Zig Bee Router (ZR)/Full Function Device (FFD)
responsible for transmitting data from device to other or
to another ZigBee Router
Zig Bee End Device (ZED)/Reduced Function Device (RFD)
contains ZigBee functionality for communication. It can talk with ZC /Z R, cannot
transmit data from one device to other directly
 targeting applications: home & industrial automation, energy management,

home control/security, medical/patient tracking, logistics and asset tracking,
Automatic Meter Reading (AMR), Smoke Detectors, HVAC control, Heat & light
Control
Specification for ZigBee is developed & Managed by ZigBee Alliance

General Packet Radio Service (GPRS):
Communication technique for transferring data over a mobile communication

network like G S M (Global System for Mobile communication)
data is sent as packets

TxDing device splits data into several related packets
At RxDing end, data is reconstructed by combining received data packets.
theoretical maximum data rate of 171.2 Kbps
radio channel is concurrently shared by several users, instead of single user.

Divides the channel into 8 time slots and data is transmitted over available channel.
77
Definition
Memory
Embedded Firmware

Embedded Firmware
 Embedded firmware refers to the control algorithm (Program instructions) and or
the configuration settings that an embedded system developer dumps into the code
(Program) memory of the embedded system.
 It is an un-avoidable part of an embedded system. There are various methods

available for developing the embedded firmware. They are listed below.
1.Write the program in high level languages like Embedded C/C++ using an Integrated
Development Environment (The IDE will contain an editor, compiler, linker,
debugger, simulator, etc.
 IDEs are different for different family of processors/controllers. For

example, Keil micro vision3. IDE is used for all family members of 805/
microcontroller, since it contains the generic 8051 compiler C51).
2.Write the program in Assembly language using the instructions supported by your
application‘s target processor/controller. The instruction set for each family of
processor/controller is different

Embedded Firmware
 The program written in either of the methods given above should be converted
into a processor understandable machine code before loading it into the program
memory.
The process of converting the program written in either a high level language or
processor/specific Assembly code to machine readable binary code is called "HE X
File Creation".
The methods used for 'HE X File Creation' is different depending on the
programming techniques used.
If the program is written in Embedded C/C++ using an IDE , the cross
compiler included in the IDE converts it into corresponding processor/controller
understandable H E X File'.
If you are following the Assembly language based programming
technique (method 2), you can use the utilities supplied by the
processor/controller vendors
to convert the source code into 'HE X File'.
Also third party tools are available, which may be of free of cost, for this
conversion.

Embedded Firmware
 For a beginner in the embedded software field, it is strongly recommended to use
the high level language based development technique.
The reasons for this being: writing codes in a high level language is easy, the code
written in high level language is highly portable which means you can use the same
code to run on different processor/controller with little or less dification.
The only thing you need to do is re-compile the program with the required
processor's IDE, after replacing the include files for that particular processor. Also
the programs written in high level languages are not developer dependent.
Any skilled programmer can trace out the functionalities of the program by just
having a look at the program. It will be much easier if the source code contains
necessary comments and documentation lines.
It is very easy to debug and the overall system development time will be reduced
to a greater extent.
The embedded software development process in assembly language is tedious and

time consuming.

Embedded Firmware
 The developer needs to know about all the instruction sets of the
processor/controller or at least he/she should carry an instruction set reference
manual with her/him.
A programmer using assembly language technique writes the program according

to his/her view and taste.
Often he/she may be writing a method or functionality which can be achieved
through a single instruction as an experienced person‘s point of view, by two or
three instructions in his/her own style.
So the program will be highly dependent on the developer. It is very difficult for a
second person to understand the code written in Assembly even if it is well
documented.
Two types of control algorithm design exist in embedded firmware development.

 infinite loop or super loop based approach
with splitting the functions to be executed into tasks and running these tasks
using a scheduler

Embedded Firmware
The first type of control algorithm development is known as the infinite loop or
super loop based approach, where
the control flow runs from top to bottom and then jumps back to the
top of the program in a conventional procedure.
It is similar to the while (1) { }; based technique in C .
The second method deals with

splitting the functions to be executed into tasks and running these
tasks using a scheduler which is part of a General Purpose or Real Time Embedded
Operating System (GPOS/RTOS).

Definition
Memory
Embedded Firmware
Other System
Components
PCB and Passive
The Components
Typical Embedded System
84
The other system components refer to the components/circuits /ICs which are
necessary for the proper functioning of the embedded system.
Some of these circuits may be essential for the proper functioning of the
processor/controller and firmware execution.
Watchdog timer, Reset I C (or passive circuit), brown-out protection I C (or

passive circuit), etc.
Some of the controllers or S o Cs integrate these components within a single I C

and doesn't require such components externally connected to the chip for proper
functioning.
Depending on the system requirement, the embedded system may include other
integrated circuits for performing specific functions, level translator ICs for
interfacing circuits with different logic levels, etc.
85
Reset Circuit:
The reset circuit is essential to ensure that the device is not operating at a voltage
level where the device is not guaranteed to operate, during system power ON.
The reset signal brings the internal registers and the different hardware systems of
the processor/controller to a known state and starts the firmware execution from the
reset vector
(Normally from vector 0x0000 for
processors/controllers. address The reset be reloc ated c onventional to
processors/controllers supporting
vector boot
can loader). an address
for
The reset signal can be either active high (The processor undergoes reset when the
reset pin of the processor is at logic high) or active low (The processor undergoes
reset when the reset pin of the processor is at logic low).
Since the processor operation is synchronized to a clock signal, the reset pulse
should be wide enough to give time for the clock oscillator to stabilize before the
internal reset state starts.
86
The reset signal to the processor can be applied at power ON through an external
passive reset circuit comprising a Capacitor and Resistor or through a standard Reset
I C like MAX810 from Maxim Dallas (www.maxim-ic.com).
Select the reset I C based on the type of reset signal and logic level (CMOS/TTL)
supported by the processor/controller in use.
Some microprocessors/controllers contain built-in internal reset circuitry and they

don't require external reset circuitry.
Figure illustrates a resistor capacitor

based passive reset circuit for active high
and low configurations.
The reset pulse width can be adjusted by

changing the resistance value R and
capacitance value C .
87
Brown-out Protection Circuit:
Brown-out protection circuit prevents the processor/controller from unexpected
program execution behavior when the supply voltage to the processor/controller falls
below a specified voltage.
It is essential for battery powered devices since there are greater chances for the
battery voltage to drop below the required threshold. The processor behavior may not
be predictable if the supply voltage falls below the recommended operating voltage. It
may lead to situations like data corruption.
 A brown-out protection circuit holds the processor/controller in reset state, when

the operating voltage falls below the threshold, until it rises above the threshold
voltage.
Certain processors/controllers support built in brown-out protection circuit which

monitors the supply voltage internally. If the processor/controller doesn't integrate a
built-in brown-out protection circuit, the same can be implemented using external
passive
88
Figure illustrates a brown-out with Active low
output circuit implementation using Zener diode and
transistor for processor/controller with active low
Reset logic,
The Zener diode Dz and transistor Q forms the heart

of this circuit. The transistor conducts always when
the supply voltage Ve is greater than that of the sum
of V B E and V Z (Zener voltage).
The transistor stops conducting when the supply voltage falls below the sum of V B E
and V Z . Select the Zener diode with required voltage for setting the low threshold
value for Vc c .
The values of R1, R2, and R3 can be selected based on the electrical characteristics
(Absolute maximum current and voltage ratings) of the transistor in use.
Microprocessor Supervisor I Cs like DS1232 from Maxim Dallas (www.maximis.com)

also provides Brown-out protection.
89
Oscillator Unit :
A microprocessor/microcontroller is a digital device made digital
combinational and sequential circuits. up of The of a
microprocessor/controller occurs in sync with a instruction
clock signal. execution
It is analogous to the heartbeat of a living being which synchronises the execution of
life. For a living being the heart is responsible for the generation of the beat whereas
the oscillator unit of the embedded system is responsible for generating the precise
clock for the processor.
 Certain processors/controllers integrate a built-in oscillator unit and simply

require an external ceramic resonator/quartz crystal for producing the necessary
clock signals. Quartz crystals and ceramic resonators are equivalent in operation,
however they possess physical difference.
 A quartz crystal is normally mounted in a hermetically sealed metal case with two
leads protruding out of the case.
90
 Certain devices may not contain a built-in oscillator unit and require the clock
pulses to be generated and supplied externally. Quartz crystal Oscillators are available
in the form chips and they can be used for generating the clock pulses in such a cases.
The speed of operation of a processor is primarily dependent on the clock frequency.

However we cannot increase the clock frequency blindly for increasing the speed of
execution.
 The logical circuits lying inside the processor always have an upper threshold value
for the maximum clock at which the system can run, beyond which the system
becomes unstable and non functional.
 The total system power consumption is directly proportional to the clock

frequency. The power consumption increases with increase in clock frequency.
 The accuracy of program execution depends on the accuracy of the clock signal.
The accuracy of the crystal oscillator or ceramic resonator is normally expressed in
terms of +/-ppm (Parts per million).
91
 Figure illustrates the usage of quartz crystal/ceramic resonator and external oscillator chip for
clock generation.
Real-Time Clock (RTC):

Real-Time Clock (RTC) is a system component responsible for keeping track of time. RTC holds
information like current time (In hours, minutes and seconds) in 12 hour/24 hour format, date,
month, year, day of the week, etc. and supplies timing reference to the system. RTC is intended to
function even in the absence of power.
92
RTCs are available in the form of Integrated Circuits from different semiconductor manufacturers
like Maxim/Dallas, ST Microelectronics etc.
The RTC chip contains a microchip for holding the time and date related information and
backup battery cell for functioning in the absence of power, in a single I C package. The RTC chip is
interfaced to the processor or controller of the embedded system.
For Operating System based em bedded devices, a timing

reference is essential for synchronizing the operations of the O S kernel.
The RTC can interrupt the OS kernel by asserting the interrupt
line of the processor/controller to which the RTC interrupt line is connected.
The O S kernel identifies the interrupt in terms of the Interrupt Request (IRQ) number
generated by an interrupt controller.
 One IRQ can be assigned to the RTC interrupt and the kernel can perform necessary
operations like system date time updation, managing software timers etc when an RTC timer tick
interrupt occurs.
 The RTC can be configured to interrupt the processor at predefined intervals or to

interrupt the processor when the RTC register reaches a specified value (used as alarm interrupt)
93
Watchdog Timer:
 In desktop Windows systems, if we feel our application is behaving in an abnormal
way or if the system hangs up, we have the "Ctrl + Alt + Del‘’ to come out of the
situation. What if it happens to our embedded system? Do we really have a "Ctrl + Alt +
Del' to take control of the situation?
 Of course not, but we have a watchdog to monitor the firmware execution and reset
the system processor/ microcontroller when the program execution hangs up
 A watchdog timer, or simply a watchdog, is a hardware timer for monitoring the

firmware execution.
 Depending on the internal implementation, the watchdog timer increments or

decrements a free running counter with each clock pulse and generates a reset signal
to reset the processor if the count reaches zero for a down counting watchdog, or the
highest count value for an upcounting watchdog.
94
 If the watchdog counter is in the enabled state, the firmware can write a
zero (for upcounting watchdog implementation) to it before starting the execution of a piece
of code (subroutine or portion of code which is susceptible to execution hang up) and the
watchdog will start counting.
 If the firmware execution doesn't complete due to malfunctioning, within the time required
by the watchdog to reach the maximum count, the counter will generate a reset pulse and
this will reset the processor (if it is connected to the reset line of the processor).
 If the firmware execution completes before the expiration of the watchdog timer you can
reset the count by writing a 0 (for an upcounting watchdog timer) to the watchdog timer
register.
 Most of the processors implement watchdog as a built-in component and provides status
register to control the watchdog timer (like enabling and disabling watchdog functioning)
and watchdog timer register for writing the count value. If the processor/controller doesn't
contain a built in watchdog timer, the same can be implemented using an external watchdog
timer I C circuit.
95
 The external watchdog timer uses hardware logic for enabling/disabling, resetting
the watchdog count, etc instead of the firmware based writing to the status and
watchdog timer register. The Microprocessor supervisor I C DS1232 integrates a
hardware watchdog timer in it.
 In modern systems running on embedded operating systems, the watchdog can be

implemented in such a way that when a watchdog timeout occurs, an interrupt is
generated instead of resetting the processor. The interrupt handler for this handles
the situation in an appropriate fashion.
 Figure illustrates the implementation of

watchdog timer:
96
Definition
Memory
Embedded Firmware
PCB and Passive

Components
97
 Printed Circuit Board (PCB) is the backbone of every embedded system. After
finalizing the components and the inter-connection among them, a schematic design
is created and according to the schematic the PCB is fabricated.
 PCB acts as a platform for mounting all the necessary components as per the design
requirement. Also it acts as a platform for testing your embedded firmware.
 Apart from the above-mentioned important subsystems of an embedded system, you

can find some passive electronic components like resistor, capacitor, diodes, etc. on
your board. They are the co-workers of various chips contained in your embedded
hardware.
 They are very essential for the proper functioning of your embedded system. For
example for providing a regulated ripple-free supply voltage to the system, a regulator
I C and spike suppressor filter capacitors are very essential.
98
For Further Studies:
Reference
Shibu K V, “Introduction to Embedded

Systems”, First Edition, McGraw Hill
Education Private
Tata Limited, 2009
52
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The Typical Embedded System: B.Thirupathi

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The Typical Embedded System

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