DIGITAL FUNDAMENTALS

LOGIC AND DIGITAL TECHNICS

 LOGIC GATES
• Logic gates or gates, are fundamental functions
performed by computers and related equipment.
• A single integrated circuit (IC) within a computer
contains several gate circuits, each gate may have
several inputs and must have only one output.
• Aircraft logic systems follow the same conventions
and standards as those used in other electronic
applications.
 LOGIC GATES CONT.
• There are six commonly used logic gates; the AND, the
OR, the INVERT, the NOR, the NAND, and the
exclusive OR. The name of each gate represents the
function it performs.
• TRUTH TABLES
• These are a systemic means of displaying binary data.
Truth tables illustrate the relationship between a logic
gate’s input and output. This type of data display can be
used to describe the operation of a gate or an IC.
• for troubleshooting purposes, the truth table for a specific IC is
often reviewed in order to determine the correct output signal
for a given set of inputs.
• Each logic gate has a symbol of a specific shape. The symbols
are designated to point at a given direction. The inputs are
always listed on the left of the symbol and the output on the
right.
• Since logic gates operate using digital data, all input and output
signals will be composed of 1s and 0s. Symbol 1 represents ON
or voltage positive and 0 OFF or voltage negative.
 LOGIC LEVEL REPRESENTATION
• When representing logic operations using Boolean algebra, each
variable can assume either a true or false value, and these values
are represented by a 1 or 0 respectively.
• When electronic switches are used to perform a logic operation it
becomes necessary to assign two discrete voltage levels that will
correspond to the binary digits of 1 and 0.
• In a logic system where the dc supply voltage is say +5v then
two choices for the voltage levels are available to represent the
binary states of 1 or 0. these are shown in the diagrams below’
• +5V- - - - - - - 1 - - - - - - - - - - - - - - -0 0---

• -0 0 - - - - - - - - - - - - - - -1 -----------

• POSITIVE LOGIC NEGATIVE LOGIC

• As can be seen that positive logic stipulates that the voltage level
assigned to the active state 1 is more positive than the level
assigned to the negative state 0. of course it can be seen that the
negative logic is the opposite i.e. the voltage level assigned to the
active state is more negative than the level assigned to the inactive
state 0.
 THE AND GATE
• An AND gate can in theory be said to consist of only two or
more switches connected in series.
• AND gates will only produce a logic 1 output when all inputs
are simultaneously at logic 1. Any other input combination
results in a logic 0 output.
• The figure below shows the symbol that represents a two input
AND gate which as can be seen, can be produced by two
switches A and B in series.
• This gate will only adopt a state at its
output terminal when both the input A
and B are also at the 1 state. As far as the
circuit is concerned, this will be the case
when both switches are closed
simultaneously .
• The AND Boolean expression given by
A.B = f.
• It should be noted that the dot between the two inputs
A and B is the way we show in Boolean algebra form
that the inputs are being ANDED together.
• The truth table for the above AND gate is shown in
the table below.
A B F = A.B

0 0 0

0 1 0

1 0 0

1 1 1
• As we proceed further, the truth table will in some cases
become quite complex especially when more than two inputs
are used.
• In all cases it is important that you write all the possible
combinations of the inputs to obtain all the possible outputs.
• You work out how many outputs are possible by realizing that it
is given by where x is the number of inputs i.e. in our case = 4.
if there are three inputs then the number of outputs is given by ,
i.e. 8 and it can be seen immediately the relatively big jump in
the number of outputs in this case.
• The easiest way to make sure all possible inputs are considered
is to determine first the number of outputs, then starting at
decimal 0, write down one line below the next in the table under
the input columns, the binary equivalent numbers consecutively
up to the number of outputs required. Consider a 3 input AND
gate and write in Boolean algebra form. A.B.C = f. there are 8
possible outputs therefore we must write down the binary
equivalents of decimal 0 to 7 as shown in the truth table.
 A B C F = A.B.C

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

• Because this is an AND gate the only state 1 output possible is

when all inputs are at state 1.
 THE OR GATE
• OR gates will produce a logic 1 output whenever any one, or more, inputs
are at logic 1. Putting this in another way, an OR gate will only produce a
logic 0 output whenever all of its inputs are simultaneously at logic 0.
• in Boolean form the function is written as f=A+ B
• As in the AND gate function, the + sign between A and B does not mean
A plus B as in ordinary algebra but A OR B. this function can be realized
by connecting two switches representing the inputs in parallel.
• Because this gate also performs the AND function when both inputs are
at 1 state, it is often referred to as an INCLUSIVE OR.
• There is need to have an OR gate which will not
perform the AND function at all and this gate is called
the EXCLUSIVE OR gate.
• The truth table below is of a 2 input OR gate;
A B F = A+B

0 0 0

0 1 1

1 0 1

1 1 1
 THE NOT GATE
• The NOT gate has one input A and one output which
is the inverse of the input. This function in Boolean
algebra form is; f = Ã
• Since there is only one input, the number of outputs
possible is = 2 and the NOT gate truth table is shown
below.

A F=Ã
0 1
1 0
 DE MORGANS RULES
• The fact is that in a doubled NOTTED expression, one NOT
cancels the other NOT
 EXCLUSIVE-OR LOGIC
• Exclusive-or gates will produce a logic 1 output whenever
either one of the two inputs is at logic 1 and the other is at logic
0.
• Exclusive-or gates produce a logic 0 output whenever both
inputs have the same logical state (i.e. When both are at logic 0
or both are at logic 1).
A B REQUIRE OUTPUT
0 0 0
0 1 1
1 0 1
1 1 0
 INVERTED INPUTS AND OUTPUTS
• The NAND and NOR gates are said to have inverted outputs. In
other words, they are equivalent to AND and OR gates with
their outputs passed through an inverter or NOT gate.
• NAND LOGIC
• NAND (i.e. NOT-AND) gates will only produce a logic 0
output when all inputs are simultaneously at logic 1. Any other
input combination will produce a logic 1 output. A NAND gate,
therefore, is nothing more than an AND gate with its output
inverted.
 NOR LOGIC
• NOR (i.e. NOT-OR) gates will only produce a logic 1
output when all inputs are simultaneously at logic 0.
Any other input combination will produce a logic 0
output.
• A NOR gate, therefore, is simply an OR gate with its
output inverted.
 SEQUENTIAL LOGIC CIRCUITS
• The fundamental elements of any digital computing system are
the gates and Bistables. A bistable is an element that has two
stable states.
• The majority have at least two inputs and two outputs, one of the
outputs is the complement of the other.
• A bistable element is a device which is capable of having its
output set by an input signal, the input signal may then be
removed but the bistable output will remain unchanged, provided
the normal power supplies are maintained.
 BISTABLE CONT.
• The bistable will store one BIT (0 or 1) of the information i.e.
the device will remember the original input condition.
• Any number of bistables can be linked together to form a
register capable of remembering any number of bits of
information.
• A bistable is often called a sequential device because its output
depends not only on the present value of inputs but also upon
the past history of the inputs and outputs.
• Bistables are the basic building blocks for counters,
registers, dividers and other sequential systems.
• It should be noted that sequential circuits can be
formed by using combinational elements and
memory.
• However the use of sequential circuits results in a
great saving of components but they are slower in
operation since in combinational circuits the
operations do not have to be performed in a sequence.
 TYPES OF BISTABLES
• There are various types of bistables; below are a few
• S-R (set-reset) bistable
• J-K bistable
• T bistable
• D bistable
• The full name of a bistable is bistable multi-vibrator
but it is also called a latch or in American terminology
a flip-flop.
 SYMBOL OF A FLIP-FLOP

• The inputs will be labeled according to the type of the flip-flop it

represents i.e. S-R, J-K etc. while the two outputs are Q and its
complement
• The value of the output Q is called the state of the flip-flop i.e.
when Q = 1, the state of the flip-flop is logic 1and when Q = 0, the
state of the flip-flop is logic 0.
• Once the state of the a flip-flop is SET, it remains this
way until changed by the input.
• THE S-R FLIP-FLOP
• This is the fundamental flip-flop and its block
diagram is shown below.
• The input leads are marked S and R which stand for set
and reset respectively.
• The signals both input and output, consist of voltage
levels which correspond to 0s and 1s.
• In all the operations we shall use the positive logic i.e
logic 1voltage level which is more positive than logic 0
level.
• If the circuit is reset, then the state of the flip-flop i.e.
the value of Q is logic 0. the state of the output will be
logic 1 when the circuit is at set.
• The S-R flip-flop can be realized by using NOR and
NAND gates with feedback loops but in both cases, the
input signal condition of S = R = 1 is not permitted.
• This is obvious because when this happens, the inputs
will be trying to set and reset the flip-flop at the same
time and the result is indeterminate.
• OPERATION
• Study the transition truth table below for the operation
of most flip-flops.
Qn Sn+1 Rn+1 Qn+1
0 0 0 0 no change
0 0 1 0 no change
0 1 0 1 SET
0 1 1 indeterminate
1 0 0 1 no change
1 0 1 0 RESET
1 1 0 1 no change
1 1 1 indeterminate
• SEQUENTIAL TRUTH TABLE
• It can be seen that the sequential truth table is a shorter version
of the transition but gives the output conditions possible for the
various values of S and R.

Sn+1 Rn+1 Qn+1 COMMENTS

0 0 0 No change
0 1 1 SET
1 0 0 RESET
1 1 ? indeterminate
• So far we have seen how various combinations of S and R
inputs determine the state of the flip-flop. If on the other hand
we know the transition tt, we should be able to deduce the input
signals required to change the state in all possible ways.
STATE OF CHANGE REQUIREMENTS
FROM TO
Qn Qn+1 S(n) R(n)
0 0 0 d
0 1 1 0
1 0 0 1
1 1 d 0
 THE S-R FLIP-FLOP USING NAND GATE
• Note that the inputs had to be complemented by
passing them through NOT gates in order for the
circuit to operate correctly.
• It can be seen from the logic circuit that inclusion of
the NOT gate between the D input and gate N2
prevents the possible input of S = R = 1.
• TRUTH TABLE
ROW PREVIOUS PREVIOUS N STATE
STATE Qn INPUT Dn Qn+1
1 0 0 0
2 0 1 1
3 1 0 0
4 1 1 1
• It can be seen that the output always follows the D
input but any change that takes place does not occur
until a clock pulse is applied as shown in the wave
form below.
 PRESET AND CLEAR
• The d-type bistable operation is thus said to be synchronous.
Additional subsidiary inputs are provided which can be used to
directly set or reset the bistable. These are usually called
PRESET (PR) and CLEAR (CLR). D-type bistables are used
both as latches (a simple form of memory) and as binary
dividers. The simple circuit arrangement together with the
timing diagram illustrate the operation of d-type bistables.
• The PRESET and CLEAR inputs are invariably both active low
(i.e. A 0 on the PRESET input will set the Q output to 1 whereas
 THE J–K FLIP-FLOP
• This is one of the most frequently used bistable and
also the most versatile. We saw that the input
combination of S = R = 1 is not permitted in an S-R ff
and even in the D type ff where there is only one
input.
• This therefore puts a limitation on these flip-flops but
in the J-K ff, it is permitted to have both inputs at
logic 1. in this condition, the state of the ff always
changes to its complement.
CIRCIUT DIAGRAM AND BLOCK DIAGRAM
• It can be seen that the outputs of two AND gates a and b now
form the inputs to the ordinary S-R ff. each of the AND gates
has three inputs.
• The a gate has the complement of the state of the ff, the j input
and the clock pulse circuit inputs. The b gate has the state of the
S-R ff, the K input and the clock pulse circuit inputs.
• Remember that as far as the S-R ff is concerned, if S = 1, the
state of the ff must be logic 1, and if R = 1, then the state of the
ff must be logic 0. we must also remember that there can only be
a logic 1 out of an AND gate when all the inputs are logic 1.
 OPERATION
• The J–k ff transition truth table and the J–K ff excitation truth
table.
PRESENT STATS PRESENT INPUTS NEW STATE Qn+1 STATE REQUIRED
CHANGE INPUTS J K
Qn Jn Kn FROM TO
Qn Jn Kn Qn+1
0 0 0 0 J K
0 1 0 1
0 0 0 d
0 0 1 0
0 1 1 1 0 1 1 d

1 0 0 1 1 0 d 1
1 1 0 1
1 1 d 0
1 0 1 0
1 1 1 0
• The d is of course the don’t care term as before, but in
this case, there are four, one in each row, as opposed
to two in the S-R ff. the more don’t care terms we
have in a truth table for a ff, the more versatile it
becomes.
• Sometimes we wish to create a change of state of a ff
at specific times, and the J-k ff can easily be modified
to produce such a circuit.
• This is called the triggered or toggled ff. it is often
abbreviated to T type ff.
 TRIGGERED OR TOGGLED (T) FLIP-FLOP
• This type of ff is constructed by merely connecting
the J and K inputs to logic 1 signal as shown in the
block diagram.
• Since J = K = 1 at the input to the ff, whenever a
clock pulse is applied, the ff must change its state.
• In our case we are assuming that it is the leading edge
of the clock pulse which initiates the triggering.
• It is seen that the first pulse leading edge at time t,
makes the ff change its state, i.e. from logic 0 to logic
1. the ff state remains at this level until the next pulse
leading edge arrives at time t. at this point the state of
the ff must change i.e from logic 1 to logic 0.
 MASTER-SLAVE FLIP-FLOP
• In this type of ff, two bistables are connected by
synchronous operated switches s1 and s2 as shown in
the block diagram.
• It can be seen that it’s impossible for both switches to be closed or
open at the same time. To achieve this in practice, the clock pulses
are fed direct to the master ff and via the inverter to the slave ff.
• This type of ff can use S-R, J-K or any other form of ff as master
and slave bistables. When used with J-K ffs, false triggering due to
internal feedback loops, which occur from time to time in S-R and
D type ffs, are prevented.
• When a clock pulse comes along, s1 is closed and the master ff
state is determined by the input conditions. The slave is isolated
from the master ff because s2 is open.
• When the clock pulse is removed, i.e. s1 opens, s2
closes and the state of the slave ff is determined by
the output of the master.
• It can be seen that the actual changes of the state of
the master-slave ff only occur on the trailing edges of
the clock pulses. This mode of operation is called
edge triggering.
 COUNTERS
• An extremely important and very widely used
application of bistables (flip-flops) is in counting.
• Counters are versatile devices which can be used for
frequency division, mathematical operations, as well
as for straight forward counting.
• They generally operate in either the synchronous or
asynchronous mode.
 SYNCHRONOUS COUNTERS
• A synchronous or parallel clocked counter is one in which all bistable
stages are clocked simultaneously, all outputs change state
simultaneously.
• ASYNCHRONOUS (RIPPLE) COUNTERS
• In this design, the bistable stages are linked together in cascade, so that
the first stage triggers the second stage, and so on through the counter.
• This type of counter can handle a high rate of data at its input, but when
the input data comes to its end , time has to be allowed for the last bit of
information applied to the input to ripple through the counter to the last
stage.
• Counters are basically sequential devices that follow a predetermined
sequence of states in response to the number of input pulses applied.
• Because the number of flip-flops used is finite for a given type of
counter,, after the maximum count has been reached, the counter
resets or stops, and the sequence is repeated.
• The most popular counter is one which has 4 stages and has a
maximum count of 11112, i.e. it counts from 0 to 15 in decimal
numbers.
• Any type of bistable can be used to construct a counter provided it is
clocked, T, J-K and D type are frequently used.
 Ripple counter block diagram.
Up-counter :- counts upward in binary.
The input clock pulse ripples through each FF. The advantage is
circuit simplicity ;& the disadvantage is low counting speed.
 SIMPLE BINARY CODED DECIMAL (BCD) COUNTER
• The total number of different states that a counter has is called the
modulus of the counter. It is usually calculated from;
• = modulus. Where n is the number of stages. In our case we had 4 stages,
the modulus would be 16, while the maximum count would be; - 1 = -1
= 15. i.e. the count is 0 -15 in decimal numbers.
• It should be appreciated that it is a quite a simple task to design a counter
whose modulus is a power of 2 i.e. 2, 4, 8, 16 etc. however we clearly
need to have counters which can count to any chosen number. In this case
we make use of a logic gate which will feed back a signal to clear the
counter at the desired point.
 A BCD counter
• Counts from 0 to 9 . It is also called decade counter or decimal counter , because
of the ten discreet states 0 through 9. It divides the input frequency by 10.

J-K FF decade counter

• It can be seen that at the count of 10 all the flip-flops have
to have output state of logic 0 i.e. and flip-flops have to be
cleared.
• If you at the BCD counter diagram, you will see that the
output of the NAND gate is logic 1 up to the time when
both of its inputs are logic 1, then its output will change to
logic 0. this occurs for the first time in the count when; and
= logic 1 i.e. after the 10th pulse. At this point, all of the
clear inputs of the flip-flops change from logic 1 to logic 0
and all of their outputs are then logic 0 and the count starts
again.
 SYNCHRONOUS BINARY COUNTER
• Is a counter in which all the ffs are synchronized to a
master timing signal known as a clock. Thus all ffs are
triggered simultaneously by a clock pulse or signal to
be counted.
• Because the change of states is at the same time ,
propagation delay is that of a single ff (delays are not
additive) ; thus much higher counting speed is
achieved.
SYNCHRONOUS BINARY COUNTER
 THE RING COUNTER
• In this type of counter, the stored logic 1 appears in
sequence at the output of each flip-flop after each
clock pulse.
• In a ring counter, the number of counts possible
equals the number of flip-flops used i.e. when there
are five flip-flops used, the count sequence is 5 (0-4).
 REGISTERS
• A register is a number of flip-flops arranged in a circuit
(typically D or J-K) used for storing data on a temporary basis.
Some registers are also capable of shifting the stored
information so that multiplication or division can be performed.
• In general all registers are designed for parallel or serial
operation. Some of the registers used in digital computers are;
• Serial input, serial output registers (SISO), Serial input, parallel
output, Parallel input, serial output, and Parallel input, parallel
output.
• Any data at input A must wait for the clock pulse to be applied
to the CP line before it can enter the register.
• Assuming the clock input is high and that a logic 1 is at input A,
the output of bistable B1 is logic 1. this then sets B2’s input to
logic 1,which in turn sets B2’s output to logic 1 and so on. All of
the input data is eventually read in during one clock pulse.
• The disadvantage with this register is that the speed of the data
transfer is into the register is uncontrolled. It would be much
better if each bit of information fed into the register is
transferred from one bistable to the next by one clock pulse.
• A total of four clock pulses would then be required to load the
4bit register.
• This can be achieved if master-slave bistables are used instead of
the simple S-R flip-flops just as we did in counter circuits.
• Much greater control may be then exercised over the contents of
the register.
• By using additional gating circuits, it is possible not only to read
in each bit of data, one clock pulse at a time, but also to shift the
data to the right or to the left under the control of the clock, such
a device is called a shift register.
 SHIFT REGISTERS
• The shift register is differs slightly from the normal storage register in
that it is capable of manipulating the information which it has stored.
• Typical examples of such manipulations are found on transferring data
from parallel form into serial form, and carrying out arithmetic al
operations in digital arithmetic units.
• Therefore shift registers are often used in conjunction with adders and
subtractors.
• It should be recalled that both division and multiplication are a form of
shifting.
 SHIFT REGISTERS
• Sometimes digital information must be sent over one wire , as
when a telephone line is used. In this case bits are sent in time
sequence or serial form.
• When digital information must be received in serial form, a shift
register may be used to accept the serial information and convert it
to parallel form..
• Use ffs as storage element, so that a bit stored can be moved or
shifted from one element to another adjacent element. All storage
registers are actuated by a single input clock or shift pulse.
• When a shift pulse is applied, the data stored in the shift register
is moved one position to the left or right.
• Shift right/left register can be used in multiplication and
division of binary numbers.
• SHIFT LEFT OPERATION.
Bits shifted from a lower order position in the number to a higher
order position causes it to multiply by 2. (i.e. bits in the binary
number shifts from right to left to multiply the number).
 SHIFT REGISTER APPLICATION

THIS CAN BE SHOWN BY THE FOLLOWING EXAMPLE.

000101 ---equals dec.5

001010 ---equals dec.10

010100 ---equals dec.20

In logic diagram: 1 0 1 0 0 0
FF1 FF2 FF3 FF4 FF5 FF6
 SHIFT RIGHT OPERATION
• Similarly, bits shifted from a higher order position to a lower
order position causes the binary number to divide by 2. (i.e. to
divide a binary number the bits must be shifted from left to
right). 11000 ---equals dec. 24
• E.g. ---equals dec. 12
01100
00110 ---equals dec. 6

In logic diagram: 0 0 0 1 1
FF1 FF2 FF3 FF4 FF5
• The storage capacity of a shift register equals the total number
of bits of digital data it can store, which in turn depends upon
the number of flip-flops used to construct the shift register.
• Since each flip-flop can store one bit of data, the storage
capacity of the shift register equals the number of Flip-flops
used.
• As an example, the internal architecture of an eight-bit shift
register will have a cascade arrangement of eight flip-flops.
SERIAL SHIFT REGISTERS
• The basic four-bit serial-in serial-out shift register implemented
using D flip-flops. The circuit functions as follows. A reset
applied to the CLEAR input of all the flip-flops resets their Q
outputs to 0s.
• The flip-flops shown respond to the low-to-high transition of
the clock pulses as indicated by their logic symbols.
• During the first clock transition, the QA output goes from logic
‘0’ to logic ‘1’. The outputs of the other three flip-flops remain
in the logic ‘0’ state as their d inputs were in the logic ‘0’ state
at the time of clock transition.
• During the second clock transition, the QA output goes from
logic ‘1’ to logic ‘0’ and the QB output goes from logic ‘0’ to
logic ‘1’, again in accordance with the logic status of the D
inputs at the time of relevant clock transition.
• Thus, we have seen that a logic ‘1’ that was present at the data
input prior to the occurrence of the first clock transition has
reached the QB output at the end of two clock transitions.
• This bit will reach the QD output at the end of four clock
transitions.
 SERIAL-IN PARALLEL-OUT SHIFT REGISTER
• A serial-in parallel-out shift register is architecturally identical
to a serial-in serial-out shift register except that in the case of
the former all flip-flop outputs are also brought out on the IC
terminals.
• Figure below shows the logic diagram of a typical serial-in
parallel-out shift register.
• Logic HIGH at either of the inputs enables the other input,
which then determines the state of the first flip-flop.
• Data at the serial inputs may be changed while the
clock input is high or low, and the register responds to
low-to-high transition of the clock.
 PARALLEL-IN SERIAL-OUT SHIFT REGISTER
• The parallel-in or serial-in modes are controlled by a shift/load
input. When the SHIFT/LOAD input is held in the logic HIGH
state, the serial data input AND gates are enabled and the circuit
behaves like a serial-in serial-out shift register.
• When the SHIFT/LOAD input is held in the logic LOW state,
parallel data input AND gates are enabled and data are loaded in
parallel, in synchronism with the next clock pulse.
 PARALLEL-IN PARALLEL-OUT SHIFT REGISTER
• The hardware of a parallel-in parallel-out shift register is similar
to that of a parallel-in serial-out shift register.
• If in a parallel-in serial-out shift register the outputs of different
flip-flops are brought out, it becomes a parallel-in parallel-out
shift register.
• In fact, the logic diagram of a parallel-in parallel-out shift
register is similar to that of a parallel-in serial-out shift register,
except that in the case of the former the flip-flop outputs have
 ANALOGUE TO DIGITAL CONVERSION
• The majority of aircraft systems and associated equipment
function on an analogue basis.
• E.g. the flight control facilities are involved with the
mechanical movement of control surfaces and the information
handled by the system concerns the factors of amplitude and
direction, which is analogue information.
• The same consideration would also apply to other systems e.g.
hydraulic, electronics, instrumentation etc.
• There is a rapidly increasing development of automatic and
built in test equipment and data recovery in modern aircraft.
• This results in a growing requirement to provide analogue
information in digital form for direct use in digital processing
systems, data transmission and telemetry.
• Analogue to digital conversion techniques must therefore be
used. There are several method available depending upon the
source of the primary information and the degree of accuracy
required.
• An analogue to digital converter (A/D) is one which changes
analogue quantities or measurements into digital numbers and
is usually called an encoder.
• The reverse process of changing digital numbers back into some
analogue form is called a decoder.
• These are generally at the input end of system to convert the
input signal into a binary code necessary for the operation of the
system.
• Encoding circuits may take many forms e.g. convert an
analogue signal to BCD or 4bit binary code; take in a binary
signal and convert it into another code to suit the system e.g.
OCTAL to BCD.
• It is an indispensable part of any digital communication system
where the analogue signal to be transmitted is digitized at the
sending end with the help of an A/D converter.
• It is invariably used in all digital read-out test and measuring
equipment. Be it a digital voltmeter or a laser power meter, or
even a ph. meter, an A/D converter is the heart of all of them.
• An A/D converter takes at its input an analogue voltage and after
a certain amount of time produces a digital output code
representing the analogue input.
• There are various techniques developed for the purpose of A/D
conversion, and these techniques have different advantages and
disadvantages with respect to one another.
• The drawing below shows a keyboard layout (decimal input) to
give a BCD output. By pressing any one key or switch (suitably
decimal numbered) the appropriate BCD code is given at the
output.
• Assume 4 is pressed then diode 5 will conduct through RC making the
output (C) go high, all the other inputs stay low, so the output is 0100
(decimal 4).
• This principle will be employed in inertial navigation systems (INS),
inertial reference systems (IRS), and flight management systems (FMS)
as all these have keyboards. So some form of encoding will convert the
input signals into the correct code for the system.
• In flight data recoding some of the input into the system are in analogue
form e.g. dc, ac or synchro signals. This means that they have to
encoded into digital for use by the central processing unit (CPU). This
is done by analogue to digital converter.