Unit 1

8086 16 bit Microprocessor

 Microprocessor
• A microprocessor is an integrated circuit (IC)
which incorporates core functions of a
computer’s central processing unit (CPU).
• Common Terms used in Microprocessor :
1) Bus :
A bus is a set of conductors intended to transmit data, address or control
information to different elements in a microprocessor. Usually a microprocessor
will have 3 types of buses : Data Bus, Control Bus and Address Bus

2) Instruction Set :
Instruction set is the group of commands that a microprocessor can understand. So
instruction set is an interface between hardware and software (program). 

3) Word Length :
Word Length is the number of bits in the internal data bus of a processor or it is the
number of bits a processor can process at a time. For eg. An 8-bit processor will
have an 8-bit data bus, 8-bit registers and will do 8-bit processing at a time. For
doing higher bits (32-bit, 16-bit) operations, it will split that into a series of 8-bit
operations.

4) Cache memory :
It is also known as CPU Memory. Cache memory is used to store data or
instructions that are frequently referenced by the software or program during the
operation. So it will increase the overall speed of the operation.
 Features of 8086 Microprocessor
• It is 16 bit microprocessor
• It has 16 bit data bus i.e it can read and write data to memory and
ports either 16 bits or 8 bits at a time
• It has 20 bit address bus i.e it can access 2^20 =10 48 576( 1 Mb)
memory location each of the 10,48,576 memory location is byte -
 16 bit words stored in two consecutive memory locations
• It has 16 bit address lines to access I/O devices , it can access
2^16 =64 K I/O locations
• It provides 16 bit registers
• it has multiplexed address and data bus AD0-AD15 and A16-A19
• 8086 is designed to operate in 2 modes i.e minimum and maximum
- It require single +5V power supply
- Clock speed range of 5-10 Mhz
- It is 16 bit processor having 16 bit ALU , 16 bit register ,
internal data bus and 16 bit external bus resulting in faster
processing
- Address ranges from 00000H to FFFFFH
- It uses 2 stages of pipelining i.e Fetch stage and Execute
Stage , which improve performance
- It fetches 6 instruction bytes from memory and queues
them in order to speed up instruction execution
Pin Description Of 8086
Concept of pipelining in 8086 microprocessor

• Technique used to enable instruction to complete each

clock cycle called as pipelining
• non pipelined processor -> 9 clock cycles required to
fetch , decode & execute  3 instruction at a time
• pipelined processor  5 clock cycle required to
fetch , decode and execute 3 instruction at time
• 1st instruction requires  3 clock cycle to complete
execution => non pipelined processor
• During 5th clock cycle I3 completing , I4 decoded , I5
being fetched =>pipelined processor
- Stack and queue concept is used stack  last in first out
and queue is first in first out
- Pipelining  improves execution speed of processor
- While executing 1st instruction in queue , 2nd instruction
decoded and remaining instruction get fetched
- Like fetch, decode & execute operation perform in
parallel i.e single clock cycle is required

Advantage :
- In pipelining ->many instruction to be executed at same
time
- Allow execution to be done in fewer cycle
- Speed up execution speed of processor
- Efficient use of processor
 I1 I1 I1 I2 I2 I2 I3 I3 I3

Clock 1 2 3 4 5 6 7 8 9
Cycle

Fetch I1 I2 I3 I4 I5

Decode I1 I2 I3 I4

I1 I2 I3
Execute

Clock Cycle 1 2 3 4 5
- 8086 has two blocks
1) Execution Unit :
- Functions of execution unit is :
i) Tell BIU where to fetch instruction or data
ii) To decode instruction
iii) To execute instruction
- Execution unit  contain control circuitry perform internal
operation
- Execution unit has 16 bit ALU  perform arithmetic & logical
operation on 8 bit or 16 bit data
- Execution unit has 16 bit flag register  that register contain 9
active flag
- Flags registers divided into 2 parts

Status Flags Control Flag

- A Flag is a flip flop which indicate some condition produced by
the execution of an instruction or control certain operation of EU

- The status flags is set /reset depending on the result of some

arithmetic or logical operation during program execution
- The control flag to control operation of CPU
 1) carry flag :
- It is set to 1 if there is carry out of MSB position i.e resulting from an addition or if a
barrow is needed at MSB during substation
- it is reset to 0 if there is no carry / barrow out of MSB bit of result

2) Auxiliary carry flag :

- If an operation performed in ALU generates a carry / barrow from lower nibble(D0-D3)
to upper nibble ( D4-D7) AF flag is set
- If no carry / barrow  AF flag is reset

3) Parity flag :
- This flag is used to indicate the parity of result
- PF is set  if lower order 8 bits of result of an operation contains even number of 1’s
- PF is reset  if lower order 8 bits of result of an operation contain odd number of 1’s

4) Zero flag :
- ZF is set  if the result of arithmetic or logical operation is zero
- ZF is reset -->if the result of arithmetic or logical operation not zero

5) Sign flag :
- In sign format  sign of number is indicated by MSB bit
- the result of operation is negative  sign flag is set
6) Overflow flag :
- OF is set  if in signed arithmetic operation , the result is too large to fit in the
numbers bits available to accommodate I
- Otherwise it is OF is reset

Control flags :
1) Trap flag:
- It is used for single step control
- allow user to execute one instruction of a program at a time for debugging
- Trap flag is set the program can be run in single step mode

2) Interrupt flag :
- It is an interrupt enable / disable flag
- It is set  mask able interrupt INTR of 8086 is enabled
- It is reset interrupt is disabled

3) Direction flag :
- It is used in string operation
- DF is set  string bytes are read or write from higher memory address to lower
memory address
- DF is reset  string bytes are read or write from lower memory address to higher
memory address
- Execution unit contain 8 16 bit general purpose registers named
as AX , BX , CX , DX , SP , BP , SI , DI
i) Data Registers
- Hold data for an operation to be performed
- There are 4 data registers( AX , BX , CX , DX )
- Instruction execute faster if the data is in a register
- Low and high bytes of the data registers can be accessed
separately
- AH, BH ,CH,DH are high bytes
- AL,BL,CL, DL are low bytes
- AX : 16 bit Accumulator register  preferred register to use in
arithmetic , logic and data transfer
- BX : 16 bit base register  servers as an address register used
in array operation
- CX : 16 bit count register used as loop counter
- DX : 16 bit data register  used to hold I/O address during I/O
instruction
2) Address registers :
- hold address of an instruction
- Segment registers : CS , DS , ES , SS
- Pointer registers : SP , BP , IP
 Bus Interface Unit
• Main function of BIU
- Fetch instruction or data from memory
- Write the data to memory
- Write the data to port
- Read data from the port

Segment Registers :
- BIU has 4 segment registers of 16 bits i.e CS ,DS , ES ,SS
i) CS (code segment ) :
- It is used to address memory location in CS where op-code of
program is stored
ii) DS (data segment ):
- It is used to point data segment of memory where data is stored
iii) ES (Extra Segment) :
- Extra segment is used to address the segment which is additional
data segment used to store the data

iv) SS (Stack Segment ) :

- It is used to point the stack location in stack segment of memory
used to store data temporarily on the stack  later used in
execution process

Instruction Queue
-To increase execution speed , BIU fetches as many as 6 instruction
bytes from memory
- When EU is busy decoding or executing current instruction , the
buses of 8086 may not in use
- At that time , BIU can use buses to fetch up 6 instruction bytes
- BIU stores these pre-fetched byes in a FIFO register called
instruction Queue
- When EU is ready for its next instruction , it simply reads the
 Memory Segmentation
• Complete physical memory is divided into a number
of logical segments in segmentation
• a segment is just an area in memory
• size of each segment is 64 kbytes  addressed one of
segments register i.e CS , DS , ES , SS
• 8086 is able to address 1 Mbytes of physical memory
divided into 16 segments each of size 64Kbytes
• The address of segments may be assigned to 0000H to
F000H
• The offset address values from 0000H to FFFFH
physical address range from 0000H to FFFFH
- The segments register contain  higher order 16 bits of the
starting address for memory segments

Advantage :
- Address associated with any instruction or data is 16 bits only
through 8086 has 20 bits physical address
- programs and data can stored separately from each others  in
segmentation
- We have programs of more than 64 Kbytes or data more than 64
Kbytes -by using more than one code or data segments
- It allow two processes to share data
- Segmentation allows you to extends the addressability of a
processor
- It allow to write programs which are position independent
- It is used in multi user time shared system
Physical memory address Generation
- 1 Mbyte (1024 Kbyte ) of physical memory can be interface with
8086 microprocessor has 20 address lines i.e 2^20 = 1024 Kbyte or
1Mbyte
- Segment register can hold 16 bit of starting address of 4 memory
segments
- 8086 has 20 bit address bus -2^20 = 1Mbyte in memory
- Address associated with any instruction or data byte is only 16 bit
called as effective address or offset or displacement or logical
address
- Logical address used to calculate physical address
- Address outputted by BIU is 20 bit called as physical address