L.1 CSE-3821 Introduction To Computer Architecture

LECTURE1:
FUNDAMENTAL OF
COMPUTER DESIGN
Dr. M. A. Rouf
Professor (Dept. Of CSE)
Dhaka University Of Engineering And Technology (DUET)
CSE-2823 Computer Architecture
Spring 2018
Email: marouf.cse@duet.ac.bd
rouf7606@gmail.com
Course Website: www.sites.google.com/a/duet.ac.bd/marouf-cse/
OUTLINE
1. Fundamentals of computers
2. Instructions of computers
3. Arithmetic of computers
4. Performance metrics
5. Datapath and control
6. Pipelining
7. Cache memory
8. Buses and I/O
9. Multi-processing introductions
10. Networking and cluster technologies
2
CSE-3821 Dr. M. A. Rouf, Dept. of CSE, DUET, Gazipur
TEXT BOOK
Textbook:
1. Computer Organization and Design: The Hardware/Software Inter-
face, 5th Edition, John L. Hennessy and David A. Patterson, Mor-
gan Kaufmann Publishers
Link:
https://drive.google.com/file/d/0B20VKNntsoafbk1od29HTTJsVDg/
view?usp=sharing
2. Computer Architecture and Organization, by John P. Hayes, Tata

McGraw-Hill Publisher

Course Website: www.sites.google.com/a/duet.ac.bd/marouf-cse/
3
COURSE TEACHERS
Instructor 1:
Dr. M. A. Rouf
Professor and Head, Dept. of CSE, DUET, Gazipur
And
Office : Old Academic Building Room: 320 or 321
Phone: Ext: 3213 (Mobile: 01711 780541)
Email: marouf.cse@duet.ac.bd, rouf7606@gmail.com
Office hours: right after class or via prior appointment

4
COURSE TEACHERS
Instructor 2:
Dr. Waliur Rahman Mia
Associate Professor, Dept. of CSE, DUET, Gazipur
Office : New Academic Building Room:
Phone: Ext: (Mobile: 01674161629)
Email:
Office hours: right after class or via prior appoint-
ments

5
GRADING POLICY
Evaluation Policy
Evaluation Type Marks
Class Attendance:
 The student with less than 60% attendance can not
attend Final Exam 30
 Can not take that course as review or backlog. The
student has to take the course in a regular semester.
Continuous Assesment and Class Performance and
Homework 60
(3 out of 4 Class test 3*20=60)
Final Exam
Section A: 105 210
Section B :105
Total 300
6
GRADING POLICY ( GRADING
SYSTEM)
Numerical Grade Letter Grade Grade Point

80% or above A Plus 4.00
75% to less than 80% A Regular 3.75
70% to less than 75% A Minus 3.50
65% to less than 70% B Plus 3.25
60% to less than 65% B Regular 3.00
55% to less than 60% B Minus 2.75
50% to less than 55% C Plus 2.50
45% to less than 50% C Regular 2.25
40% to less than 45% D 2.00
Less than 40% F 0.00
7
ATTENDANCE POLICY
Attendance Marks
90% or above 30
85% to less than 90% 27
Less than 60% 0 ( and can not attend final
exam)
8
NOTICE
Late attending in class will be considered as zero
attendance.
Late submission of homework is considered as zero
marks in the continuous assessment.
Absent in the class without information will not be
considered any more.
The students whose average percentage of attendance
is less than 75% in any of the theory, lab/sessional /field
work courses for which he/she has registered in one
academic year shall not be eligible for the award of any
type of scholarship/stipend/grant for the following
academic session.
9
SINGLE PROCESSOR PERFORMANCE
10
11
CURRENT TRENDS
Cannot continue to exploit Instruction-Level parallelism (ILP)
• Single processor performance improvement ended in 2003
New models for performance:

• Data-level parallelism (DLP)
• Thread-level parallelism (TLP)
• Request-level parallelism (RLP)
• These require explicit restructuring of applications
12
CLASSES OF
COMPUTERS
Personal Mobile Device (PMD)
• e.g. smart phones, tablet computers
• Emphasis on energy efficiency and real-time for media apps
Desktop Computing
• Emphasis on price-performance
13
CLASSES OF
COMPUTERS (CONTD..)
Servers
•
Emphasis on availability, scalability, throughput
•
Clusters / Warehouse Scale Computers
•
Used for “Software as a Service (SaaS)”
•
Emphasis on availability and price-performance
•
Sub-class: Supercomputers, emphasis: floating-point
performance and fast internal networks
Embedded Computers
• Microwaves, washing machines, printers, networking
switches
• Emphasis: price
14
PARALLELISM
Classes of parallelism in applications:
• Data-Level Parallelism (DLP)
• Task-Level Parallelism (TLP)
Classes of architectural parallelism:
• Instruction-Level Parallelism (ILP)
• Exploit DLP
• Vector architectures/Graphic Processor Units (GPUs)
• Exploit DLP
• Thread-Level Parallelism
• Exploit DLP or TLP
• Request-Level Parallelism
• Exploit TLP
15
LAYER OF SYSTEM ARCHITECTURE
16
LAYER OF SYSTEM ARCHITECTURE
Apps Applications – Generic Software

hardware
O/S Operating System – Controlling Software
Arch Architecture – HW/SW Interface
software
mArch marchitecture – High-level organization
Logic Digital Logic – Building-block Modules
Digital Digital Circuits – Continuous  Discrete
Analog Analog Circuits – Fun with Electricity
Devices Devices – Transistors, Capacitors, etc.
Physics Physical Properties – Electrons, Ions, etc.
17
ANALOG CIRCUITS – ELECTRONS IN
MOTION
Apps s d
s
O/S
g The NMOS
Arch Transistor
d
mArch
Logic
s g s g
d d
Digital
Analog
Devices
Physics
18
DEFINING COMPUTER
ARCHITECTURE
The task of computer designer:
Determine what attributes are important for a new
computer, then design a computer to maximize performance
while staying within cost, power, and availability constrains
19
DEFINING COMPUTER
ARCHITECTURE
This task has many aspects:
• Instruction set design
• Functional organization
• Logic design
• And implementation
Also,
• Integrated circuit design
• Packaging
• Power
• Cooling
AND
• Optimization, including a lot of technologies (complier, OS…)
20
MOORE’S LAW
No. of transistors
Generation Year
THE POWER OF MINIATURIZATION
EDSAC 1 (1949) Pentium 4 (2002)

~ 500 OPs ~ 12 GFLOPs
(Giga floating point operations per second)
22
24,000,000 times faster
INSTRUCTION SET
ARCHITECTURE (ISA)
The instruction set architecture
serves as the boundary between
the software and hardware.
23
INSTRUCTION CODE
FORMAT
Instruction code format with two parts : Op. Code + Address
• Op. Code : specify 16 possible operations(4 bits)
• Address : specify the address of an operand(12
bits)
• If an operation in an instruction code does not need
an operand from memory, the rest of the bits in the
instruction(address field) can be used for other
purpose
15 12 11 0 15 12 11 0
Op. Code Address data
24
instruction
Not an instruction
COMPONENTS OF INSTRUCTIONS
Operations (opcodes)
Number of operands (Number of data locations)
opcode:add value in src1 to

value in src2 and place the add r1,r2,r3
result in dst.
opcode src1 src2 dst
ADD R1, R2, R3 R1  R2 + R3
Instruction encodings
25
TRENDS IN
TECHNOLOGY
To evaluate a computer, designer must
be aware of rapid changes in
implementation technology
• Integrated circuit logic:
• transistor density increase by about 35% per year
• Increase in die size is ranging from 10% to 20%
per year
• The combined effect is a growth rate in transistor
count on a chip is about 40%~55% per year
26
TRENDS IN
TECHNOLOGY
• DRAM (dynamic random-access memory):
• Capacity increases by about 40% per year, doubling
roughly every two years
• Magnetic disk technology

• Before 1990: 30% per year, doubling in 3 years
• 1996~2004: from 60% to 100% increase per year
• After 2004: drop back to 30% per year
• Despite this roller coaster of rates of improvement, it is
still 50-100 times cheaper than DRAM
• Flash Memory
27

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LECTURE1:

2. Computer Architecture and Organization, by John P. Hayes, Tata

Numerical Grade Letter Grade Grade Point

New models for performance:

Apps Applications – Generic Software

EDSAC 1 (1949) Pentium 4 (2002)

Op. Code Address data

opcode:add value in src1 to

ADD R1, R2, R3 R1  R2 + R3

• Magnetic disk technology

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