Analog and Digital Electronics

21CS33
Venugopala Rao A S
Dept. of Computer Science and Design
AIET, Moodbidri
 LATCHES & FLIP-FLOPS
• Difference between Flip-flop and Latch

Flip-flop is a bi-stable device i.e., Latch is also a bi-stable device

it has two stable states that are whose states are also represented
represented as 0 and 1 as 0 and 1.
It checks the inputs but changes
It checks the inputs continuously
the output only at times defined
and responds to the changes in
by the clock signal or any other
inputs immediately.
control signal.
It is a edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND,
NAND are building blocks of flip These are also made up of gates.
flops.

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They are classified into
asynchronous or synchronous
It forms the building blocks of
many sequential circuits like
counters.
Flip-flop always have a clock
signal
Flip-flop can be build from
Latches
e.g. :D Flip-flop, JK Flip-flop
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There is no such classification in
latches.
These can be used for the
designing of sequential circuits but
are not generally preferred.
Latches doesn’t have a clock
signal
Latches can be build from gates
e.g. : SR Latch, D Latch
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 LATCHES & FLIP-FLOPS
• EDGE-TRIGGERED D FLIP-FLOP
• A D flip-flop has two inputs, D (data) and Ck (clock).
• The flip-flop output changes only in response to the clock,
not to a change in D.
• If the output changes in response to a 0 to 1 transition on the
clock then it is called positive edge triggered flip-flop.
• If the output changes in response to a 1 to 0 transition on the
clock, then it is called negative edge triggered flip-flop.

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 LATCHES & FLIP-FLOPS
• The term active edge refers to the clock edge (rising or
falling) that triggers the flip-flop state change..
• Truth table:

• Working
• The Q output of the flip-flop is the same as the D input,
except that the output changes are delayed until after the
active edge of the clock pulse

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• Timing Diagram (Falling edge clock is considered)

• Construction:
• A rising-edge-triggered D flip-flop can be constructed from
two gated D latches and an inverter, as shown in the
following Figure

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• Analysis:

• When CLK = 0, G1 = 1, and the first latch is transparent so that the P output
follows the D input.
• Because G2 = 0, the second latch holds the current value of Q.
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• When CLK changes to 1, G1 changes to 0, and the current
value of D is stored in the first latch.
• Because G2 = 1, the value of P flows through the second
latch to the Q output.
• When CLK changes back to 0, the second latch takes on the
value of P and holds it and, then, the first latch starts
following the D input again.
• If the first latch starts following the D input before the
second latch takes on the value of P, the flip-flop will not
function properly.

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• Therefore, designers must pay careful attention to timing
issues when designing edge-triggered flip-flops.

• With this circuit, output state changes occur only following

the rising edge of the clock.

• The value of D at the time of the rising edge of the clock

determines the value of Q, and any extra changes in D that
occur between rising clock edges have no effect on Q.

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• W.k.t. A flip-flop changes state only on the active edge of the
clock
• Propagation delay of a flip-flop is the time between the
active edge of the clock and the resulting change in the
output.
• There are timing issues associated with the D input.
• To function properly, the D input to an edge-triggered flip-
flop must be held at a constant value for a period of time
before and after the active edge of the clock.
• If D changes at the same time as the active edge, the
behavior is unpredictable.
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 LATCHES & FLIP-FLOPS
• The amount of time that the D input must be stable before the
active edge is called the setup time (tsu)
• The amount of time that the D input must hold the same value
after the active edge is the hold time (th).

• The times at which D is allowed to change during the clock cycle

are shaded in the timing diagram
• The propagation delay (tp) from the time the clock changes until
the Q output changes is also indicated in the above Figure
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