Floorplanning

Vipin Kizheppatt 22/03/20231

 Floorplanning
After partitioning area and connectivity information about each block is known

In floorplanning, location and dimensions of these blocks are decided

Input to floorplan  set of blocks, area of blocks, possible shapes, number of

terminals and netlist

Output  location and shape of each block

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 Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed

A C
B

A B
C

A
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 Example
Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed

This floorplan has a global bounding box with minimum possible area (9 square units). 4
 Floorplanning Terminologies
Fixed blocks: Blocks for which dimensions are known

Flexible blocks: Blocks for which dimensions have to be determined

Placement problem: Problem of assigning locations to fixed blocks on layout

surface

Floorplanning: Placement problem becomes floorplanning problem if one or

more blocks are flexible

Chip planning: Planning of interconnect in addition to floorplanning

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 Floorplanning Terminologies
I/O Pads Floorplan
Module a

Module b
Block a Block c
Module c
GND VDD
Chip Block d
Planning Block Pins
Block
Module d b Block e

Module e

Supply Network 6
 Optimizations of Floorplanning
Minimize area of the global bounding box
 Global bounding box of a floorplan is the minimum axis-aligned rectangle that contains
all floorplan blocks.
 Area of the global bounding box represents the area of the top-level floorplan
Minimize Total wirelength
 Long connections between blocks may increase signal propagation delays in the design
Combination of area area(F) and total wirelength L(F) of floorplan F
 Minimize ∙area(F) + (1 – )∙L(F)
where the parameter 0 ≤  ≤ 1 gives the relative importance between area(F) and L(F)

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 Factor Considered for Floorplanning
Shape of blocks
 To simplify the problems all blocks are assumed to have rectangular shape
 Floorplanner uses aspect ratio to determine the shape (height/width)
 Usually there will be an upper and lower bound on aspect ratio
Routing considerations
 Blocks need to be placed in such a way that there is sufficient routing area between them
Packaging considerations
 Blocks which generate maximum heat should be placed farther
Preplaced Blocks
 Locations of some blocks may be prefixed

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 Slicing Floorplan
Obtained by repeatedly dividing each rectangle, starting with the entire
chip area, into two smaller rectangles
Horizontal or vertical cut line
A slicing tree or slicing floorplan tree is a binary tree with k leaves and k –
1 internal nodes
 Each leaf represents a block
 Each internal node represents a horizontal or vertical cut line

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 Slicing Floorplan

V V

c H H H H
b

e f a b c H a b d H
a
d d V c V

e f e f

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 Slicing Floorplan
Polish expression

c H H
b

e f a b c H A B+ C D EF ++ 
a
d d V

e f

· Bottom up: V   and H  +

· Length 2n-1 (n = Number of leaves of the slicing tree) 11
 Non-slicing Floorplan

b b
c a
e e
a c
d d

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 Integer Programming based Floor Planning
Ref: Suphachai Sutanthavibul and Eugene Shragowitz, “An Analytical Approach to Floorplan
Design and Optimization”, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. 10, No.
6, JUNE 1991

MILP formulation wi

wj

hj Module j
hi Module i

(xj,yj)

(xi,yi)

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 Constraints to prevent overlapping
wi
wj

hj Module j
hi Module i xi + wi ≤ xj

(xj,yj)

(xi,yi) wi

wj

hj Module j hi Module i
xi - wj ≥ xj
(xj,yj)
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(xi,yi)
Constraints to prevent overlapping
wj

hj Module j

(xj,yj)
wi

y i + hi ≤ y j
hi Module i

(xi,yi)

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Constraints to prevent overlapping
wi

hi Module i

(xi,yi) y i - hj ≥ y j
wj

hj Module j

(xj,yj)
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 Constraints to prevent overlapping
xi + wi ≤ xj i is to the left of j
xi - wj ≥ xj i is to the right of j
yi + hi ≤ yj i is below j
yi - hj ≥ yj i is above j

But only one of these constraints need to be true at a time (but at least one
should be true)

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Constraints to prevent overlapping
xi + wi ≤ xj + W(xij + yij)
xi - wj ≥ xj - W(1-xij + yij)
yi + hi ≤ yj + H(1+xij-yij)
yi - hj ≥ yj - H(2-xij – yij)

xij and yij are binary variables

W and H are bounding values such that
|xi-xj| ≤ W and |yi-yj| ≤ H

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Constraints to prevent overlapping
xi ≥ 0 for all i
yi ≥ 0
xi+wi ≤ W
y* ≥ yi + hi

Where y* has to be minimized

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