Flip-Flops & Latches

This presentation will

• Review sequential logic and the flip-flop.
• Introduce the D flip-flop and provide an excitation
table and a sample timing analysis.
• Introduce the J/K flip-flop and provide an excitation
table and a sample timing analysis.
• Review flip-flop clock parameters.
• Introduce the transparent D-latch.
• Discuss flip-flop asynchronous inputs.
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Sequential Logic & The Flip-Flop
Inputs . . Outputs
. Combinational .
Logic Gates

Memory
Elements
Clock (Flip-Flops)

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 NAND GATE LATCH
• The NAND gate latch or simply latch is a basic FF.
• The two NAND gates are cross-coupled
• The inputs are set and clear (reset)
• The inputs are active low, that is, the output will change when the input is
pulsed low.

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NAND GATE LATCH (Cont.)

NAND latch Truth Table

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NAND GATE LATCH (Cont.)

NAND latch Truth Table

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NOR GATE LATCH

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NOR GATE LATCH (Cont.)
Q Waveform

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Clock Signals and Clocked FFs
Clock

A clock pulse is a time varying voltage signal applied to control the operation
(triggering) of a flip flop.
When the clock changes from a 0 to a 1, this is called the positive-going transition
(PGT)
When the clock changes from a 1 to a 0, this is called the negative-going transition
(NGT)

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Clock Signals and Clocked FFs (Cont.)

Clocked FFs have a clock input that is typically labeled CLK, CK or CP.

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 Setup and Hold Times
Setup time is the amount of time required for the input to a Flip-Flop to be
stable before a clock edge. Hold time is similar to setup time, but it deals with
events after a clock edge occurs.
Hold time is the minimum amount of time required for the input to a Flip-
Flop to be stable after a clock edge.

Propagation delay is the amount of time it takes for signals to pass between two
Flip-Flops. Clock frequency,

tclk (min) = tsu + th + tp

Q. If you have a 50 MHz clock, 1 ns setup time, and 2 ns hold time, what will
your design allow for its maximum propagation delay between two flip-flops?

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 Flip-Flop Timing
1
Data Input
(D,J, or K)
0

tS tH
Setup Time Hold Time
Positive 1
Edge
Clock 0

Setup Time (tS): The time interval before the active transition of the clock
signal during which the data input (D, J, or K) must be maintained.

Hold Time (tH): The time interval after the active transition of the clock
signal during which the data input (D, J, or K) must be maintained.
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S-C Flip-Flop: Excitation Table

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D Flip-Flop: Excitation Table

D Q
D CLK Q Q
0  0 1

CLK Q 1  1 0

 : Rising Edge of Clock

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 D Flip-Flop: Example Timing

Q=D=1 Q=D=0 Q=D=0 Q=D=1 Q=D=1 Q=D=0 Q=D=0

No Change No Change No Change

CLK

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J/K Flip-Flop: Excitation Table

J K CLK Q
J Q
0 0  Q0 No Change
CLK
0 1  0 Clear
K Q
1 0  1 Set

1 1  Q0 Toggle

 : Rising Edge of Clock

Q : Complement of Q

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 J/K Flip-Flop: Example Timing

NO NO
SET TOGGLE TOGGLE CLEAR CHANGE SET CHANGE

CLK

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 Clock Edges
Positive Edge Transition

Negative Edge Transition

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 Asynchronous Inputs
Asynchronous inputs (Preset & Clear) are
used to override the clock/data inputs and
PR
force the outputs to a predefined state.
D Q
The Preset (PR) input forces the output to:
Q 1 & Q  0
CLK Q
The Clear (CLR) input forces the output to: CLR

Q  0 & Q 1
PR CLR CLK D Q Q
PRESET CLEAR CLOCK DATA

1 1  0 0 1
1 1  1 1 0
0 1 X X 1 0 Asynchronous Preset
1 0 X X 0 1 Asynchronous Clear
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0 0 X X 1 1 ILLEGAL CONDITION
 D Flip-Flop: PR & CLR Timing
Q=D=1 Q=D=0 Q=D=0 Q=D=1 Q=D=1 Q=D=0
Clocked Clocked Clocked Clocked Clocked Clocked

Q
Q=1 Q=1
Preset Preset

PR Q=0
Clear

CLR

CLK

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Asynchronous Inputs

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 Flip-Flop Vs. Latch
• The primary difference between a D flip-flop and
D latch is the EN/CLOCK input.
• The flip-flop’s CLOCK input is edge sensitive,
meaning the flip-flop’s output changes on the
edge (rising or falling) of the CLOCK input.
• The latch’s EN input is level sensitive, meaning
the latch’s output changes on the level (high or
low) of the EN input.

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 Master/slave FFs
• The Master-Slave Flip-Flop is basically a
combination of two JK flip-flops connected
together in a series configuration.

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 Master/slave FFs
Working of a master slave flip flop –
1.When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the
state of the system. The slave flip-flop is isolated until the CP goes to 0. When the CP
goes back to 0, information is passed from the master flip-flop to the slave and output
is obtained.
2.Firstly the master flip flop is positive level triggered and the slave flip flop is negative
level triggered, so the master responds before the slave.
3.If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and
the clock forces the slave to reset, thus the slave copies the master.
4.If J=1 and K=0, the high Q output of the master goes to the J input of the slave and
the Negative transition of the clock sets the slave, copying the master.
5.If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave
toggles on the negative transition of the clock.
6.If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

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Flip-Flops & Latches
74LS74
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear, and Complementary Outputs

74LS76
Dual Negative-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs

74LS75
Quad Latch

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74LS74: D Flip-Flop

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74LS76: J/K Flip-Flop

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74LS75: D Latch

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