Introduction To Vlsi Technology

Introduction to VLSI
Technology
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VERY LARGE SCALE INTEGRATION
Is the science of integrating millions of transistors

on a Silicon Chip.

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VLSI IN INDUSTRY AN EXAMPLE

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EVOLUTION IN COMPUTERS
First Computer (ENIAC)

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VLSI - RECENT DEVELOPMENTS
 Nanometer technology 0.5u, 0.35u, 0.25u, 0.18u, 0.13u,
90nm, 65 nm ….
 Higher Operating Speeds Crossing Giga Hz.
 Voltage Migration
5V, 3.3V, 2.5V, 1.8V, 1.5V, 1V …

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EVOLUTION OF PROCESSORS
Processor 4004 8008 8080 8086 8088
Introduced 11 / 15 / 71 4 / 1 / 72 4 / 1 / 74 6 / 8 / 78 6 / 1 / 79
Clock Speeds 108 KHz 200 KHz 2 MHz 5 MHz, 8 MHz, 5 MHz, 8
10 MHz MHz
Bus Width 4 bits 8 bits 8 bits 16 bits 8 bits
Number of 2,300 3,500 6,000 29,000 29,000

Transistors (10 µ) (10 µ) (6 µ) (3 µ) (3 µ)

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Processor 80286 Intel 386 DX Intel 386 SX Intel 486
DX CPU
Introduced 2 / 1 / 82 10 / 17 / 85 6 / 16 / 88 4 / 10 / 89
Clock Speeds 6, 8, 10, 12.5 16, 20, 25, 33 16, 20, 25, 33 25, 33, 50 MHz
MHz MHz MHz
Bus Width 16 bits 32 bits 16 bits 32 bits
Number of 134,000 275,000 75,000 1.2 million

Transistors (1.5 µ) (1 µ) (1 µ) (1 µ)
( .8 µ @ 50MHz)

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Processor Intel 486 SX Pentium Pentium Pro Pentium II

Introduced 4 / 22 / 91 3 / 22 / 93 11 / 01 / 95 5 / 07 / 97
Clock Speeds 16, 20, 60, 66 MHz 150, 166, 180, 200, 233, 266, 300
25, 33 MHz 200 MHz MHz
Bus Width 32 bits 64 bits 64 bits 64 bits
Number of 1.185 million 3.1 million 5.5 million 7.5 million

Transistors (1 µ) (.8 µ) (0.35 µ) (0.35 µ)
Pentium – IV has 43 million transistors and uses 0.13 µ

technology.
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HOW DOES IT LOOK LIKE
TODAY ?

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PENTIUM® III DIE - 0.18µ TECHNOLOGY

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SILICON WAFER
 A single silicon wafer
holds many dies.
 Wafer specifications
Thickness - 300 µ
Diameter - 8 inches.
 New fabs use 12”

Diameter

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APPROXIMATE SIZE RELATIONSHIP
Processor Transistors Processor Transistors

8085 6 µ 6,000 P-I 0.5 µ 5.5 million
8086 3 µ 29,000 P-II 0.35 µ 7.5 million

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What is the end product ?
VLSI

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VLSI- Advantages
 Integration improves the design:
– lower parasitic’s = higher speed;
– lower power;
– physically smaller.
 Integration reduces manufacturing cost-
(almost) no manual assembly.

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ADVANTAGES OF VLSI
 Increase in
 Reduction in
– Operating Speed
– Design cycle time
– Design Security
– Product Size
– Productivity
– Power Consumption
– Design Flexibility
– Cost

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VLSI Design
ISSUES CHALLENGES
 Design Methodology
 Rate of change of
 Time To Market technology Vs Design cycle
 Clock Speed time
 Power Consumption  Feature Size Vs Modeling
 Cost & Testing
 Silicon Technology  Speed Vs Power

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THE GOAL OF IC DESIGNER
 Meet the market requirement

 Satisfying the customers needs
– Beating The competition
– Increasing the functionality
– Reducing the cost
 Achieved By
– Using the next generation Silicon Technologies
– New Design Concepts & Tools
– High Level Integration

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VLSI - FAMILY IN THE PRESENT DAY
CONTEXT
 VLSI family consists of

– PLD’s
– ASIC’s
– Full Custom devices
– EDA Tools.
– IP Cores – Soft IC’s
Explosion in Technology in all the above has changed the

VLSI Design scenario.
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WHAT IS PROGRAMMABLE LOGIC ?
 Programmable Logic Consists of,
– Simple Programmable Logic Devices (SPLDs)
– Complex Programmable Logic Devices (CPLDs)
– Field Programmable Gate Arrays (FPGAs)

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CPLD or FPGA?
 CPLD
 FPGA
 Non-volatile
 SRAM reconfiguration
 JTAG Testing
 Excellent for computer
architecture, DSP,
 Wide fan-in registered designs
 Fast counters, state  ASIC like design flow
machines
 PROM required for non-
 Combinational Logic volatile operation
 Small student projects,  Fair Sized Project
lower level courses Implementations

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FPGA Architecture – in details

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FPGA - General Structure
Logic block Interconnection switches
I/O block
I/O block
I/O block
I/O block

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Simplified Configurable Logic Block (CLB)
Diagram
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Configurable Logic Block (CLB) Diagram,
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from Xilinx XC4000 series da
FPGA - Basic SRAM Logic Block
Select
Out
Flip -flop
In1
D Q
In2
LUT
In3
In4
C lock

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FPGA - Look-Up Tables
A LUT can be used to code any Boolean function of the

inputs (unlike PLD’s)
Mainly used in SRAM based FPGA’s to code combinational

logic
G1
Z
G2
LUT
G3
G4

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LUT - Two Input Example
x1 x2 f1
0 0 1
0 1 0
1 0 0
1 1 1
Before Programming After Programming
x1
x1
1
0/1
0
0/1 f1
f
0
0/1
1
0/1
x2
x2

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Implementation of a Combinational
Function using 4-Input LUT
A A B C D Out
B
Out
C
0 0 0 0 0
D 0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
A
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
Out 0 1 1 1 1
B 1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
C 1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
D

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Programmable Interconnects
LB LB LB
Switch Switch
Matrix Matrix
LB LB LB

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Development Process
Specification Synthesis
Generic
HDL or Netlist
Schematics
Technology
Mapping
Device
Device Place and Dependent
Configuration Route Netlist
Bit stream
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FPGA Evaluation

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WHAT ARE ASICS..?
 ASICs are silicon chips that have been designed for a specific
application. Putting in other words, it is a chip designed to perform a
particular operation as opposed to general purpose integrated circuits:
 An ASIC is NOT software programmable to perform different tasks.
 ICs that are not ASICs are :

– DRAM, SRAM, 8085
Silicon Die
 ICs which are ASICs:
– Baseband processor in mobile phone
– Chipsets in PCs
– MPEG encoders/ decoders
– DSP functions in hardware, e.g. FFT

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WHY USE ASICs?
 Requirements :
– Greater Complexity, Increased Performance
– Higher Density, Lower Power Dissipation
– Shorter Time-to-Market (TTM)
– Cheaper in large quantities
 ASIC’s can be broadly classified as

– Full custom ASIC
– Semi custom ASIC

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FULL CUSTOM ASIC
 When engineers have a specific application to be designed and they are

bothered about the performance, speed, power and cost, they go for
designing Full Custom ASIC.
 The circuit is partitioned into a collection of sub-circuits according to some

criteria such as functionality. Which are laid out specifically for one chip.
 Every transistor is designed and drawn by hand.
 Typically only way to design analog portions of ASICs.
 Usually used for layout of microprocessors.
 Full-custom design is very time consuming; thus the method is inappropriate

for very large circuits, unless performance is of utmost importance

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SEMI CUSTOM ASIC
 All mask layers are customized - transistors and interconnect
– Automated buffer sizing, placement and routing
 Custom blocks can be embedded
 Manufacturing lead time is about eight weeks.

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EDA TOOLS THE THIRD ARM
 EDA - stands for Electronic design Automation
 EDA Tools are the software programs that make the

design flow happen.
e.g. Simulator, Synthesizer, Schematic Editor …etc
 EDA tools are the most important aspects of VLSI

Design and in the present day context, VLSI design is
totally dependent upon EDA Tools.

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BACKBONE OF VLSI DESIGN
Backbone of VLSI design are, Industries
like….
EDA Companies
 Mentor Graphics
 Synplicity
 Synopsys
 Cadence
 Aldec……
Device Vendors
 Xilinx, Altera , Actel, Cypress,
QuickLogic …etc

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EDA TOOLS: Design Entry
 VIEWlogic – a ( ViewDraw - a hierarchical schematic capture
and block diagram tool)
 Mentor Graphics ( Renoir )
 Cadence Design Systems
 OrCAD
 ALDEC ( Active-HDL )
 Simucad ( Silos-3 )
 Protel
 Tanner Research ( L-Edit Pro 8.4 )
 Capilano Computing Systems ( DesignWorksTM )
 Capfast Morphologic ( rapid-development system )
 MyCAD

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EDA Tools :Design Simulation
 Mentor Graphics ( Modelsim )
 Synopsys
– VCS™ ( High performance Verilog Simulation )
– Sirocco™ ( High performance VHDL Simulation )
 Cadence
– - Verilog XL Simulator
– - DRACULA - The Physical Verification Standard
 Simucad ( Silos-III )
 SynaptiCAD - TestBencher Pro - Timing Diagram & Testbench
Generation Software
 Quickturn Design Systems ( PowerSuite™ )
 VIEWlogic ( Fusion/SpeedWave - a VHDL simulator)
 Diagonal Systems ( BestBench )

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EDA TOOLS : Logic Synthesis &
Optimization
 Synopsys
– FPGA Express
– FPGA Compiler
 Synplicity – ( Synplify )
 Mentor Graphics - ( LeonardoSpectrum )
 VIEWlogic – ( IntelliFlow )
 Cadence Design Systems
 Aldec – ( ACTIVE synthesis )
 Accolade Design Automation
 Logical Devices
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Programmable Logic Vendors
 Xilinx - Spartan II, Saprtan3, Virtex-II, Virtex-IIPro, Virtex4
( Software : ISE 8.1i )
 Altera - FLEX, APEX, MAX, Cyclone, CycloneII, Stratix
( Software : Quartus II, MAX+II )
 Lattice - ispEXPERT Compiler
 Actel - Actel's Designer Series FPGA Development System
 Atmel - FPGA Integrated Development System (IDS)
 QuickLogic - QuickWorks
 Triscend – Configurable System-on-Chip Devices
 ST Microelectronics - MCU peripherals + programmable logic

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WHAT IS CORE ?
 Are also called as IP-Cores.
 They are big business and a hot
issue.
 They can be looked upon as “Soft
IC’s”.
 They Reduce Time for Design &
Verifications
 Are Optimized by Device

vendors,
– Hence offer Best possible
Device utilization
– Help achieve,
 Better Overall System
Performance
 Fast Time To Market

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IP Cores
Defining IP
 Pre designed modules are called Intellectual Property (IP) Cores or Virtual
Components (VC)
 Main concept is reuse of existing designs
 IP cores allow design teams to rapidly create large system-on-a-chip designs
(SOCs) by integrating pre-made blocks that do not require any design work
or verification
 IP cored reduce the possibility of failure based on design and verification of
a block for the first time
Why IP’s???
 Savings in time and cost to produce more complex designs when using third-
party IP cores
 Ease of integration for available IP cores into more complicated systems
 Commercially available IP cores are pre-verified and reduce the design risk
 Significant improvement to the product design cycle

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IP Core Categories
IP Cores
Firm Cores
Hard Cores Soft Cores
Hard IP Cores
 Hard IP cores consist of hard layouts using particular physical design libraries
and are delivered in masked-level designed blocks
 These blocks are designed to be as efficient as possible in terms of power
consumption, silicon real estate and performance
 Hard cores offer optimized implementation and the highest performance for
their chosen physical library
 Integration of hard IP cores is quite simple and the core can be dropped into
an SOC physical design with minor integration effort
 However, hard cores are technology dependent and provide minimum
flexibility and portability in reconfiguration and integration across multiple
designs and technologies
 A hard core is very technology-specific

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IP Core Categories - Soft IP Cores
 Soft IP cores are delivered as RTL VHDL/ Verilog code to provide
functional descriptions of IPs
 These cores offer maximum flexibility and re-configurability to
match the requirements of a specific design application
 But these must be synthesized, optimized, and verified by their user
before integration into designs
 It is technology independent. VHDL or Verilog doesn’t require the
use of a specific process technology or standard cell library. This
means same IP can be used for multiple designs
 Soft cores are subsequently synthesized down into a group of PLBs
(possibly combined with some hard IP blocks like multipliers,
adders etc)
 It’s not possible for the provider to support all the potential libraries

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IP Core Categories - Firm IP Cores
 Firm IPs balance the high performance and optimization properties
of hard IPs with the flexibility of soft IPs
 These cores are delivered in the form of targeted netlists to specific
physical libraries after going through synthesis without performing
the physical layout
 It also comes in the form of a library of high level functions, but
these functions have already been optimally mapped, placed and
routed into a group of PLBs
 One or more copies of each predefined firm IP block can be
instantiated into the design as required
Hard Low
Soft
Firm High
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IP Sources
 The three main sources of IP are
– Internally created blocks from previous designs
– FPGA vendors
– Third party IP providers (Cast, Virtual IP Group ..etc)
 IP Core Generators- These generators are special tools that act as IP
block/core generators
– IP generators are almost invariably parameterized, allows
designers to specify parameters like depths, widths, or both of
buses and functional elements
– It also allows to select a list of functional elements that designer
wish to include or exclude from final representation
– Helps designer to create the most efficient IP block/core in terms
of its resource requirements and performance
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CORE SOLUTIONS APPLICATIONS
 Base Level Functions
Microprocessors, Microcontrollers, UART, Other Peripherals.
 Standard interface - PCI, USB, FIREWIRE, Ethernet MAC …etc,
 DSP Functions - Filters, MAC, FFT, Cordic …etc
 Telecom & Networking - ATM, SONNET…etc
 Xilinx Supplies more than 1000 types of Free cores with their Software
packages.

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VLSI
HOW DO YOU DO IT ?

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Design Entry text
text text
Functional
Simulation
Synthesis
Gate Level
Simulation
Mapping + Translatio
Timing n
Simulation
Place & Route
Programming

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DESIGN ENTRY
 Design entry is the media through which idea’s with designer are
entered into the soft format.
 There are various ways in which the design can be entered. Some of
the popular one’s are :
– Designing with the help of schematics.
– Designing using HDL’S [ Hardware Description Language ].
– Designing using State Machines.

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DESIGN ENTRY
SCHEMATIC HDL CODING FSM
“C” “Java”
4 input AND gate

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DESIGN ENTRY
 Hardware Description Languages : An effective way to describe the
functionality in a user friendly manner
– VHDL
– [ Very High Speed Integrated Circuit Hardware Description
Language ].
 Origin : 1981 (DOD America)
 Standard : IEEE1076 –1999
– VERILOG
 Standard : IEEE1364

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DESIGN ENTRY
SCHEMATIC HDL CODING FSM “C” “Java”
Use library ieee;

use ieee.std_logic_1164.all;
entity AND4 is
port (
A, B, C,D : in std_logic;
S : out std_logic;
);
end AND4 ;
architecture AND4 _ARCH of AND4 is
begin
S <= (A and B) and (C and D) ;
end AND4_ARCH;
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DESIGN ENTRY
 SCHEMATIC HDL CODING FSM “C”

“Java”
STATE MACHINE TO COUNT THE SEQUENCE

001 - 011 - 111
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RTL MODEL
 Register Transfer Level Model :
Functionality is described as flow of data
in between the registers

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Simulation Purpose
 Analyze a Design / Testbench for Correct Syntax
 Elaborate the Design for Integrity
 Run the Testbench
 Observe that the Design Behaves as Expected
 Saves the time consuming need for physical prototyping

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FUNCTIONAL SIMULATION
 Functional Simulation is carried after entering the design.
 Need for the simulation comes from the fact that the entered design
is working as per specifications
 Advantage : Saves the time consuming need for physical prototyping
A
B
C=1
D=1

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Functional simulation of 4-input and gate
SYNTHESIS
 Synthesis is automatic process of converting HDL code into equivalent logic
gates.
 Synthesis results are Target Technology Dependent.
 Works on the principle that any function can be implemented using NAND.
Use library ieee;
use ieee.std_logic_1164.all;
entity AND4 is
port (
A, B, C,D : in std_logic;
S : out std_logic;
);
end AND4 ;
architecture AND4 _ARCH of AND4 is
begin
S <= (A and B) and (C and D) ;
end AND4_ARCH;

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SYNTHESIS
Constraint
Design Libraries
Synthesis
Netlist Report

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Different Implementations of 4-
i/p Gate

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SYNTHESIS – ADVANTAGE HDL
The code is synthesized into a counter,

Advantages:
• Easy and logical way of describing a counter in HDL.
• Easily scalable architecture.
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POST-SYNTHESIS SIMULATION
 Post Synthesis also called as GATE Level Simulation
Simulation verifies functionality after Synthesis.
 Need - Synthesis programs may implement HDL code in different way than
expected.
Post synthesis simulation of 4-input and gate
A
B
C=1
D=1 Models gate
S delays
S1
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GATE DELAY
PLACE & ROUTE
 Is the process of,
– Placing the design into the
specified Device.
– Optimizing the usage of
available resources, viz.
logic cells and Interconnects.
 Is Vendor and Target Technology
Dependent
 It Uses
– Vendor Libraries
Vendor ???
– Algorithms
– Directives
– User Specified Constraints
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4-INPUT AND GATE – AFTER P&R

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POST P & R SIMULATION
 Post P&R Simulation verifies functionality after place and route
 Need - Interconnect delays are known at this stage only.
B
C=1
D= 1
S1
S2

GATE DELAY
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INTERCONNECT DELAY
Others
PROGRAM & SYSTEM TEST
 Programming is the process of downloading the design into the
device. Applicable only for PLD’s
 After the device is programmed, you are ready to test the actual
system, with real life inputs and outputs.
DESIGN LIBRARIES
 Are pre-Compiled design units. Of standard functions.
 Are stored in a design library.
 Are generally specified by Device Vendors, come as a part of their
package.
 Also Designers can store components designed by them as library
components to achieve design reuse.

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VLSI - APPLICATIONS
 VLSI Finds applications in all aspects of Life,
 Consumer Electronics, Defense, Computers, Communication, Space,
Networking…..
 Some of applications could be listed as

– WIRELESS LAN
– RE - CONFIGURABLE COMPUTING
– WEARABLE COMPUTERS
– HOME NETWORKING
– BLUETOOTH
– SONET / SDH
– Bus Interfaces, viz. PCI, Firewire, USB

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WIRELESS LAN - NO WIRES
Digital Camera
Computer
Scanner
Inkjet
Printer
Home Audio System PDA Cordless Phone

Cell Phone Base Station
MP3
Player
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VLSI OPPORTUNITES
IBM Logic Eastern Wipro
Intel Sasken L&T
Motorola GE DCM
Texas Instruments HCL Mos Chip
ST MicroElectronics SCL Chip Engines
Powai Labs Synopsys U&I Scotty
Insight [ Xilinx] PMC Sierra Sage
Philips Siemens Synopsys
Sanyo IKOS Cirrus Logic
Lucent Alliance Semiconductor Cadence
Avnet Mentor Graphics Synplicity
Nu-horizons
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JOB AVENUES
 More than 400 companies in India working in VLSI

design
 More then 100 Companies in Bangalore itself.
 Major Hubs - Bangalore, Delhi, Hyderabad, Chennai,
Pune, Mumbai.
 Salaries in the range of 2 to 4 lacs/annum.
 Jobs are for Design Engineer, Test Engineer, Field
Application Engineers, Backend .

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Introduction to VLSI

Copy rights©Powai Labs Tech. Pvt.Ltd.

Is the science of integrating millions of transistors

Copy rights©Powai Labs Tech. Pvt.Ltd.

Copy rights©Powai Labs Tech. Pvt.Ltd.

First Computer (ENIAC)

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 Higher Operating Speeds Crossing Giga Hz.

Copy rights©Powai Labs Tech. Pvt.Ltd.

Number of 2,300 3,500 6,000 29,000 29,000

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Number of 134,000 275,000 75,000 1.2 million

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Processor Intel 486 SX Pentium Pentium Pro Pentium II

Number of 1.185 million 3.1 million 5.5 million 7.5 million

Pentium – IV has 43 million transistors and uses 0.13 µ

Copy rights©Powai Labs Tech. Pvt.Ltd.

Copy rights©Powai Labs Tech. Pvt.Ltd.

 New fabs use 12”

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Processor Transistors Processor Transistors

8086 3 µ 29,000 P-II 0.35 µ 7.5 million

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Copy rights©Powai Labs Tech. Pvt.Ltd.

Copy rights©Powai Labs Tech. Pvt.Ltd.

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 Meet the market requirement

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 VLSI family consists of

Explosion in Technology in all the above has changed the

– Simple Programmable Logic Devices (SPLDs)

– Complex Programmable Logic Devices (CPLDs)

– Field Programmable Gate Arrays (FPGAs)

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Copy rights©Powai Labs Tech. Pvt.Ltd.

Copy rights©Powai Labs Tech. Pvt.Ltd.

Copy rights©Powai Labs Tech. Pvt.Ltd.

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A LUT can be used to code any Boolean function of the

Mainly used in SRAM based FPGA’s to code combinational

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Before Programming After Programming

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 An ASIC is NOT software programmable to perform different tasks.

 ICs that are not ASICs are :

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 ASIC’s can be broadly classified as

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 When engineers have a specific application to be designed and they are

 The circuit is partitioned into a collection of sub-circuits according to some

 Every transistor is designed and drawn by hand.

 Typically only way to design analog portions of ASICs.

 Usually used for layout of microprocessors.

 Full-custom design is very time consuming; thus the method is inappropriate

Copy rights©Powai Labs Tech. Pvt.Ltd.

Copy rights©Powai Labs Tech. Pvt.Ltd.

 EDA Tools are the software programs that make the

 EDA tools are the most important aspects of VLSI

Copy rights©Powai Labs Tech. Pvt.Ltd.