M E M O RY M A N A G E M E N T

Questions
• Consider a paging hardware with a TLB. Assume that the entire page table and
all the pages are in the physical memory. It takes 10 milliseconds to search the
TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is
0.6, the effective memory access time (in milliseconds) is _________.

As both page table and page are in physical memory T(eff) = hit ratio * (TLB access time +
Main memory access time) + (1 - hit ratio) * (TLB access time + 2 * main memory time) =

0.6*(10+80) + (1-0.6)*(10+2*80) = 0.6 * (90) + 0.4 * (170) = 122

• Consider a machine with 64 MB physical memory and a 32-bit virtual address space.
If the page size is 4KB, what is the approximate size of the page table?

Physical Address Space = 64MB = 2^26B

Virtual Address = 32-bits, ∴ Virtual Address Space = 2^32B
Page Size = 4KB = 2^12B
Number of pages = 2^32/2^12 = 2^20 pages.

Number of frames = 2^26/2^12 = 2^14 frames.

∴ Page Table Size = 2^20×14-bits ≈ 2^20×16-bits ≈ 2^20×2B =

2MB.
• In a virtual memory system, size of virtual address is 32-bit, size of physical
address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-
bit. The main memory is byte addressable. Which one of the following is the
maximum number of bits that can be used for storing protection and other
information in each page table entry?

Virtual memory = 232 bytes Physical memory = 230 bytes

Page size = Frame size = 4 * 103 bytes = 22 * 210 bytes =
212 bytes
Number of frames = Physical memory / Frame size =
230/212 = 218
Therefore, Numbers of bits for frame = 18 bits
Page Table Entry Size = Number of bits for frame + Other
information Other information = 32 - 18 = 14 bits
• A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a
translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is
4-way set associative. The minimum size of the TLB tag is:
• https://cs.nyu.edu/~gottlieb/courses/2000s/2001-02-fall/arch/lectures/lecture-22.html

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• A computer uses 46–bit virtual address, 32–bit physical address, and a three–
level paged page table organization. The page table base register stores the
base address of the first–level table (T1), which occupies exactly one page.
Each entry of T1 stores the base address of a page of the second–level table
(T2). Each entry of T2 stores the base address of a page of the third–level
table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits
in size. The processor used in the computer has a 1 MB 16 way set associative
virtually indexed physically tagged cache. The cache block size is 64 bytes.
What is the size of a page in KB in this computer? (GATE 2013)

Let the page size is of 'x' bits
Size of T1 = 2 ^ x bytes
(This is because T1 occupies exactly one page)
Now, number of entries in T1 = (2^x) / 4
(This is because each page table entry is 32 bits
or 4 bytes in size)
Number of entries in T1 = Number of second level
page tables
(Because each I-level page table entry stores the
base address of page of II-level page table)
Total size of second level page tables = ((2^x) / 4) *
(2^x)
Similarly, number of entries in II-level page tables =
Number
of III level page tables = ((2^x) / 4) * ((2^x) / 4)
Total size of third level page tables = ((2^x) / 4) *
((2^x) / 4) * (2^x)
Similarly, total number of entries (pages) in all III-level
page tables = ((2^x) / 4) * ((2^x) / 4) * ((2^x) / 4)
= 2^(3x - 6)
Size of virtual memory = 2^46
Number of pages in virtual memory = (2^46) / (2^x) = 2^(46 - x)
Total number the pages in the III-level page tables =
Number of pages in virtual memory
2^(3x - 6) = 2^(46 - x)
3x - 6 = 46 - x
4x = 52
x = 13
That means, page size is of 13 bits
or Page size = 2^13 bytes = 8 KB