Verilog HDL 18EC56

Module 3
Gate-Level Modeling,
Dataflow Modeling
Dinesh M.A.
dineshma_ece@mitmysore.in
•
/dinesh.ajay
/prof.dineshma
 VISION OF THE DEPARTMENT

• To be recognized by the society at large as

offering Value based Quality Education to
groom the next generation entrepreneurs,
leaders and researchers in the field of
Electronics and Communication to meet the
challenges at global level.

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 MISSION OF THE DEPARTMENT

• To groom the students with strong foundations of Electronics and

Communication Engineering and to facilitate them to pursue higher
education and research.
• To educate and prepare the students to be competent to face the challenges of
the industry/society and /or to become successful entrepreneurs.
• To provide ethical and value-based education by promoting activities
addressing the societal needs.
• Enable students to develop skills to solve complex technological problems of
current times and also provide a framework for promoting collaborative and
multidisciplinary activities.

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 Program Educational Objectives (PEOs)

• Be able to have a successful career in dynamic industry

that is global, multidisciplinary, and evolving.
• Solve problems, design and innovate while they work
individually or in teams with sense of  professional ethics
and social responsibility.
• Communicate effectively and manage resources skillfully
as members and leaders of the profession

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 Program Specific Outcomes (PSOs)

• An ability to apply the basic concepts of engineering

science into various areas of Electronics Communication
Engineering.
• An ability to solve complex Electronics and
Communication Engineering problems, using state of the
art hardware and software tools, along with analytical
skills to arrive at cost effective and efficient solutions.

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 Course Outcomes
CO’s DESCRIPTION OF THE OUTCOMES

Present the comprehension of the IC Design flow, syntax, lexical

18EC56.1 conventions, data types, system tasks compiler directives and logic
synthesis in Verilog HDL.
Develop Verilog modules for digital circuits using gate level and
18EC56.2 data flow modeling, behavioral modeling using different control
structures and related statements and for system tasks as well.
Analyze the behavior of structural, dataflow and behavior modeling
18EC56.3
procedures written in Verilog.
Design digital functional blocks for a given set of specifications
18EC56.4
using hierarchical modeling concepts in Verilog.

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 RBT
Module – 3 Level
Gate-Level Modeling: Modeling using basic
Verilog gate primitives, description of and/or
and buf/not type gates, rise, fall and turn-off
delays, min, max, and typical delays. L1, L2,
L3
Dataflow Modeling: Continuous assignments,
delay specification, expressions, operators,
operands,operator types.

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 Chapter 5
Gate-Level Modeling

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 Primitive Gates in Verilog:
And/Or Gates

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 And/Or Gates Examples

• Syntax
• Similar to module instantiations
• Examples
wire out, in1, in2, in3;

and a1(out, in1, in2);

nand na1(out, in1, in2);

nand na1_3inp(out, in1, in2, in3);

and (out, in1, in2); // Legal gate instantiation. No need to instance name.

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Verilog HDL 03/06/2023 11
 Buf/Not Gates

• Exactly one input, but multiple outputs

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 Buf/Not Gate Examples
// basic gate instantiations.
buf b1(OUT1, IN);
not n1(OUT1, IN);

// More than two outputs

buf b1_2out(OUT1, OUT2, IN);

// gate instantiation without instance name

not (OUT1, IN); // legal gate instantiation

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 Bufif/Notif Gates

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 Bufif/Notif Examples

//Instantiation of bufif gates.

bufif1 b1 (out, in, ctrl);
bufif0 b0 (out, in, ctrl);

//Instantiation of notif gates

notif1 n1 (out, in, ctrl);
notif0 n0 (out, in, ctrl);

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 Arrays of Gate Instances
• Multiple instantiations • Array of instances
wire [7:0] OUT, IN1, IN2; wire [7:0] OUT, IN1, IN2;
nand n[7:0](OUT, IN1, IN2);
nand n0(OUT[0], IN1[0],IN2[0]);
nand n1(OUT[1], IN1[1],IN2[1]);
nand n2(OUT[2], IN1[2],IN2[2]);
nand n3(OUT[3], IN1[3],IN2[3]);
nand n4(OUT[4], IN1[4],IN2[4]);
nand n5(OUT[5], IN1[5],IN2[5]);
nand n6(OUT[6], IN1[6],IN2[6]);
nand n7(OUT[7], IN1[7],IN2[7]);

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 Examples: 4-to-1 Multiplexer

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 Examples: 4-to-1 Multiplexer (cont’d)
module mux4_to_1 (output out, input i0, i1, i2, i3, s1, s0);
wire s1n, s0n;
wire y0, y1, y2, y3;

not (s1n, s1);

not (s0n, s0);

and (y0, i0, s1n, s0n);

and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);

or (out, y0, y1, y2, y3);

endmodule

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 module stimulus;
Stimulus reg IN0, IN1, IN2, IN3;

Block reg S1, S0;

wire OUTPUT;
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
initial
begin
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);

S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end
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endmodule
 Examples: 4-bit ripple-carry full adder
module fulladd(output sum, c_out,
input a, b, c_in);

wire s1, c1, c2;

xor (s1, a, b);

and (c1, a, b);

xor (sum, s1, c_in);

and (c2, s1, c_in);

xor (c_out, c2, c1);

endmodule
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 Examples: 4-bit ripple-carry full adder (cont’d)

module fulladd4(
output [3:0] sum,
output c_out,
input [3:0] a, b,
input c_in);

wire c1, c2, c3;

// Instantiate four 1-bit full adders.

fulladd fa0(sum[0], c1, a[0], b[0], c_in);

fulladd fa1(sum[1], c2, a[1], b[1], c1);

fulladd fa2(sum[2], c3, a[2], b[2], c2);

fulladd fa3(sum[3], c_out, a[3], b[3], c3);

endmodule

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 module stimulus;

Stimulus reg [3:0] A, B;

reg C_IN;
Block wire [3:0] SUM;
wire C_OUT;

fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

initial
$monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b,
SUM= %b\n“, A, B, C_IN, C_OUT, SUM);

initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
#5 A = 4'd2; B = 4'd5;
#5 A = 4'd9; B = 4'd9;
#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
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endmodule
Delay Models and
Gate Level Delays
 Delay Models

• Transport Delay Model

• Path delay, Pin-to-pin delay, propagation delay

• Inertial Delay Model

• Input Inertial delay
• Output Inertial delay

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 Gate Delays in Verilog
• Rise delay

• Fall delay

• Turn-off delay
• Delay for value change to x
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 Specifying Gate Delay
// Delay of delay_time for all transitions
and #(delay_time) a1(out, i1, i2);

// Rise and Fall Delay Specification.

and #(rise_val, fall_val) a2(out, i1, i2);

// Rise, Fall, and Turn-off Delay Specification

bufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);

Examples:

and #(5) a1(out, i1, i2); //Delay of 5 for all transitions

and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control);
// Rise = 3, Fall = 4, Turn-off = 5

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 Min/Typ/Max Delay values
• Can be separately specified for each delay type
// One delay
// if +mindelays, delay= 4
// if +typdelays, delay= 5
// if +maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);

// Two delays
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);

// Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
bufif0 #(2:3:4, 3:4:5, 4:5:6) a3(out, in, ctrl);

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 Delay Example
module stimulus;

reg A, B, C;
wire OUT;

D d1( OUT, A, B, C);

initial
begin
A= 1'b0; B= 1'b0; C= 1'b0;
#10 A= 1'b1; B= 1'b1; C= 1'b1;
#10 A= 1'b1; B= 1'b0; C= 1'b0;
#20 $finish;
end

endmodule

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 Text

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