VLSI & Microelectronics

Paper Code:EC601
(Module1 : Lecture 6)
Intended Audience : B-Tech (ECE) ,3rd Year, (Section :A+B) ,6th Sem
Dr. Surajit Bari
Assistant Professor , ECE Department ,Narula Institute of Technology, An
Autonomous Institute Under JIS Group , Affiliated to MAKAUT, WB
Ph.D.(Tech-MAKAUT,WB) , M-Tech (JU), B.E.(BU)
MIEEE(CAS , EDS) ,MIEI
E-mail: surajit.bari@nit.ac.in , Mob No. 8240925284/9432128450
 VLSI & Microelectronics

Module 1 : Lecture 6
Classification of IC: Standard IC and ASIC, FPGA
Architecture
 Outlines

 Category of IC : Standard IC and ASIC

 Classification of ASIC
 Comparison of Different ASIC Design Style
 FPGA Architecture
 Q & A Session
 Summary
 References
 Category of IC : Standard IC and ASIC

What is Standard IC ?
 Standard IC or general purpose ICs are used for many purpose applications. These are
used for wide range of applications

 For example microprocessor IC ; memory IC:ROM ; DRAM ; OP-AMP IC ;Timer IC etc.

What is Application Specific IC ( ASIC) ?

 Application Specific Integrated Circuits are used for some specific applications

 Some example of ASIC : IC for satellite , chip to run a cell phone ,chip used for voice
recorder , chip for toys , chip for washing machine , Chip in a DVD Player to decode the
information or an optical disc , an IC designed as a charge controller for Lithium Ion
batteries etc.
 Category of IC : Standard IC and ASIC

 ASICs have more functionality , consume less power , are used for faster applications
compared to standard IC or general purpose ICs

 Since the early 1980s, the world of integrated circuits has been highly influenced by ASICs

 ASICs are responsible for the expansion of the semiconductor industry . It is possible to
change in the business model of the integrated circuits. And ASIC causes significant
increase in IC designs and design engineers

 ASICs have also influenced the whole ecosystem of the semiconductor design and
manufacturing like system design, fabrication and manufacturing process, testing and
packaging and also the CAD tools
 Classification of ASICs

 Depending on the application, cost of production, performance, and the

volume of production, there are different VLSI design styles which are
followed to implement a chip

 Each of the styles has its own advantages and disadvantages

 Different design style are chosen for the requirement of target

application

 Based on the design style, ASICs are classified in different groups

Classification of ASICs
 Classification of ASICs : Full-Custom Design

Full-custom Design
 In the full-custom design, the designers do not use the pre-designed standard cell library

 Instead, they design the entire chip from the scratch

 As each and every part is designed in this approach, the chips are highly optimized for
area, power, and delay

 Hence, a full-custom design is always superior to any other design style

 However, full-custom design cycle time is higher compared to other design styles

 Full-custom design style is used for high performance and high volume products
 Classification of ASICs : Semi-Custom Design

Semi-custom Design
 In this style of design, almost all the basic building blocks are used
from the standard cell library

 Only few cells are designed from the beginning, which are not
available in the standard cell library or to be optimized for a specific
target

 This approach is faster compared to the full-custom style

 Classification of ASICs : CBIC

Standard Cell-Based Design ( CBIC: Cell Based IC)

 The standard cell-based integrated circuit refers to a class
of integrated circuits which uses the pre-designed, pre-
tested, and pre-characterized standard cells

 The standard cells include basic logic gates (AND, OR,

NAND, NOR, XOR, XNOR, NOT, etc.), some mega cells
(such as multiplexer, full-adder, decoder, etc.)

 Also includes sequential elements (such as D Flip-Flop ,

Flip-Flop with direct set/reset/clear inputs, registers, etc.), Fig. Standard Cell Based
input–output buffers (I/O cells), and some special cells. Architecture

 All these standard cells are designed, tested, and

characterized and put in a database which is known as a
standard cell library
 Classification of ASICs : CBIC

 In the standard cell-based architecture, the standard cells are placed in rows to build the
integrated circuit chip

 The ASIC designer defines only the placement of the standard cell and the interconnect in
a CBIC

 However, this design style also includes the already designed mega modules or fixed
blocks (Pre designed ) . These blocks are also known as full-custom block ,cores ,system
levels macros

 The main advantages of CBICs is that designer able to save time , money and risk by using
predesigned , pretested and pre-characterized standard cell library

 In addition each standard cell can be optimized individually

 Classification of ASICs : CBIC

 Disadvantage in CBIC design are

(a) time or expense of designing or buying the standard cell library
(b) time needed to fabricate all layers of ACIC for new design
 Classification of ASICs : Gate Array Based Design

Gate Array Based Design

 In a gate array (GA) structure, the transistors are predefined/fabricated on the silicon wafer

 But the interconnections are not fabricated

 The metal mask layers are customized to define the interconnections between the transistors for
a targeted functionality

 It can also be used for the prototype development in short time

 Depending on the array structure, the GA are of the following three types: (a) Channelled (b)
Channel-less ( c) Structured
 Classification of ASICs : Gate Array Based Design

 In the channelled gate array

architecture, there are rows of
transistors called arrays and
channels are provided between the
rows of transistors for their
interconnections

Fig. Channelled Architecture

 Classification of ASICs : Gate Array Based Design

 In the channel-less gate array there are no

channels between the rows

 As there are no channels in the channel-less

architecture, the interconnections are made
by drawing metal lines through the unused
transistors

Fig. Channel-less Architecture

 Classification of ASICs : Gate Array Based Design

 In case of the structured GA

architecture, either channelled or
channel-less structure can be used,
but the only difference is that it
includes custom blocks

Fig. Structured gate array architecture

 Classification of ASICs : Programmable Logic Devices (PLDs)

PLDs
 Programmable logic devices (PLDs) are standard products, which can be
programmed to obtain the desired functionality required for a specific application

 The programming can be done either by the end user or by the manufacturer

 The PLDs which are programmed by the manufacturer are known as mask-
programmable logic devices (MPLDs)

 The PLDs, which are programmed by the end user are called field-programmable
logic devices (FPLDs)
 Classification of ASICs : Programmable Logic Devices (PLDs)

 The PLDs have wide range of applications and have low risk ,PLDs are
cheaper

 As the PLDs are pre-manufactured, tested, and placed in inventory in

advance, the design cycle time is very short

 The PLDs are classified into three categories based on the architecture
and programmability
(a) Read only memory (ROM)
(b)Programmable Array Logic (PAL)
(c)Programmable Logic Array (PLA)
 Classification of ASICs : Programmable Logic Devices (PLDs)

ROM
 Read only memory (ROM) is a
memory chip which can be
programmed once to store
binary data

Fig. 8×4 ROM architecture

PAL
 Programmable array logic (PAL) is another programmable architecture which can be
programmed to implement the desired function
 The PAL architecture is shown in Fig.
 It has a programmable AND array or plane followed by a fixed OR array or plane PAL also
includes flip-flops so that it can be used to design state machines.
 The AND array is programmed to generate the product terms or literals of the Boolean
functions to be implemented and then ORed by the OR plane to generate the functions

Fig. PAL architecture

 Classification of ASICs : Programmable Logic Devices (PLDs)

PLA
 In contrast to the PAL,
programmable logic array
(PLA) has both programmable
AND array and OR array

 The AND array is

programmed to generate the
product terms and then ORed
by programming the OR array Fig. PLA architecture
 Classification of ASICs : FPGA

Field Programmable Gate Array (FPGA)

 Field programmable gate array (FPGA) is a fully
fabricated IC chip in which the interconnections
can be programmed to implement different
functions

 An FPGA chip has thousands of logic gates which

are to be connected to implement any logic
function

 A typical FPGA architecture is shown in Fig

 It has the following three main components: (a) I/O

Fig. FPGA architecture
buffers (b) Array of configurable logic blocks (CLBs)
(c) Programmable interconnects
 Comparison of Different ASIC Design Style

Table 1 : Comparison of Design Style

Full-Custom Standard Cell-Based Gate Array FPGA

Area Small Small to moderate Moderate Large

Performance High High to moderate Moderate Low

Fabrication Layers All All Metal layers None

Design Time High High to moderate Moderate Low

 Comparison of Different ASIC Design Style

Comparison of different design styles based on logic cells and

interconnections

Full-Custom Standard Cell- Gate Array FPGA PLDs

Based
Cell size Variable Fixed height Fixed Fixed Fixed
Cell type Variable Variable Fixed Programmable Programmable

Cell placement Variable In row Fixed Fixed Fixed

Interconnection Variable Variable Variable Programmable Programmable

 FPGA: Introduction

 Field programmable gate array  (FPGA) is an IC which can be hardware-

programmed to implement various logic functions

 The end users of FPGA can program it to configure for any functionality—so
it is called field programmable

 FPGA is completely fabricated and standard parts are tested and available
readily for use.

 FPGA can be used for prototyping of an idea into silicon in a very short time
 Basic Architecture of FPGA

 There are a number of different

FPGA architecture

 Basically, it contains three

major components

 (a)configurable logic block (CLB)

(b) switch matrix (c) IOB

 A simple FPGA architecture is

shown in Figure
 Types of FPGA Programming : Antifuse-based , EPROM-based , SRAM-based

 There are three types of FPGA programming technology

 Antifuse-based , EPROM-based , SRAM-based

Antifuse-based
 The antifuse FPGAs are programmed by applying high voltage between the
two terminals of the fuse to break down the dielectric material of the fuse

 The antifuse switch used in FPGA is shown in Figure

 Antifuse structure is normally used in an open circuit condition

 However, when they are programmed a low resistance path is established

 Types of FPGA Programming : Antifuse-based

 As shown in Figure the top and bottom layers are conducting, and the middle layer is an
insulator

 In normal conditions, the insulating layer isolates the top and bottom layers

 But when the antifuse is programmed, a low resistance path is established through the
insulator

Fig. Antifuse switch (a)

schematic(b) structure
 Types of FPGA Programming : Antifuse-based

 The antifuse switches have smaller on-resistance and parasitic capacitance than pass transistors and
transmission gates

 Hence, it supports higher switching speed

 Antifuse switches are one-time programmable, so design changes are not possible

Fig. Antifuse switch (a)

schematic(b) structure
 Types of FPGA Programming : EPROM-Based

EPROM Based
 The FPGAs use EPROM and EEPROM technology which are programmed using high voltages

 The devices are reprogrammable and nonvolatile, and can  be programmed while the devices are embedded in the
system

 The EPROM and EEPROM programming is based on the flash memory cell

Fig. (a) Switch interconnection (b)

EPROM flash memory cell
 Types of FPGA Programming : EPROM-Based

 Flash memory cell uses two gates, one is the control

gate and another is the floating gate

 Under normal mode of operation, there are no

charges on the floating gate, and the transistor
behaves like a normal transistor with low threshold
voltage

 When a high voltage is applied to the control gate,

the floating gate is charged, and the threshold
voltage is increased
Fig. (a) Switch interconnection (b)
EPROM flash memory cell
 The transistor becomes permanently OFF
 Types of FPGA Programming : SRAM-Based Switch Matrix

SRAM Based Switch Matrix

 In the SRAM-based FPGA, the logic functions are
based on the stored bits in the SRAM

 These devices use CMOS transmission gates for

switching

 The interconnect switch fabric is shown in Figure

 Each crosspoint has six switches, which are

controlled by the SRAM

 Depending on the bit stored in the SRAM, the

connection is established between the horizontal and
the vertical inter connect wires
 Types of FPGA Programming : SRAM-Based

 For example, in the figure the

north-to-east (NE) connection is
established by the SRAM
containing a bit 1

 This makes the nMOS transistor

ON, and the connection between
N and E is established.
 Configurable Logic Block(CLB)

 The configurable logic blocks (CLBs) contain several

modules such as lookup tables (LUT), multiplexers,
gates, and flip-flops

 LUT is a hardware that stores the truth table of a

function in an SRAM to function as a combinational
circuit

 Figure shows an SRAM-based LUT

 As shown in Figure , the 8 × 4 SRAM architecture

Fig.: SRAM based LUT
implements the 3-input and 4-output combinational
logic
 Configurable Logic Block(CLB)

 The SRAM is used, because of reprogramming the memory so that

different functions can be implemented

 But as the SRAM is volatile memory, the stored data gets erased
once the power goes off
 Input –Output Block :IOB
 A Configurable input/output (I/O) Block, as shown
in Figure , I/O block is used to bring signals onto
the chip and send them back off again

 It consists of an input buffer and an output buffer

with three-state and open collector output
controls

 Typically there are pull up resistors on the outputs

and sometimes pull down resistors that can be
used to terminate signals and buses without
requiring discrete resistors external to the chip
Fig. Configurable I/O Block [3]
 Input –Output Block :IOB

 The polarity of the output can usually be programmed for

active high or active low output, and often the slew rate of the
output can be programmed for fast or slow rise and fall times

 There are typically flip-flops on outputs so that clocked signals

can be output directly to the pins without encountering
significant delay, more easily meeting the setup time
requirement for external devices

 Similarly, flip-flops on the inputs reduce delay on a signal

before reaching a flip-flop, thus reducing the hold time
requirement of the FPGA
Fig. Configurable I/O Block [3]
 FPGA Based System Design Flow

 A typical FPGA-based system design flow is

shown in Figure

 The flow starts with the design specifications

 The functional description of the system is

written in a hardware description language
(VHDL or Verilog) in the behavioural modelling
style

 The functionality is checked by performing

behavioural simulation using a set of test
vectors

 The next step is to perform synthesis

 FPGA Based System Design Flow

 The synthesis step translates the behavioural

netlist into a gate level netlist

 The synthesis step requires the  behavioural

netlist, the selected device family (e.g.,
Spartan, Virtex) name, and other synthesis
directives

 The gate level netlist is again checked for

functionality

 The user constraints are to be specified for

timing, power, etc.

 Then using the user constraints and gate level

netlist, the implementation step is performed
 FPGA Based System Design Flow

 In the implementation step, the

mapping of the logic gates are done to
the available functional blocks in the
FPGA

 The placement and routing are done to

complete the implementation

 Next, the bitstream file is generated

which contains the programming data

 The bitstream file is downloaded

through the JTAG cable into the FPGA
device
 FPGA Based System Design Flow

 Downloading the bitstream

into the FPGA device is often
referred to as FPGA
programming

 The final step is to test the

FPGA device in the system, and
debug for any problems in
functionality
 Q & A Session

Q1. What do you mean by ASIC ?

Q2 . What is standard IC ?

Q3. What are different ASIC design method ?

Q4 . Make a comparison of different ASIC design style

Q5. What is FPGA?

Q6. Describe the FPGA architecture .

Q7. Describe SRAM based programing mechanism in FPGA

Q8. Write down the steps of FPGA design .

 Summary

 Standard IC & ASIC

 ASIC design Style : full-custom , semicustom ,CBIC, GA , PLDs , FPGA
 Comparison of ASIC design style
 Architecture of FPGA
 References
[1] VLSI Design , Debaprasad Das , Oxford

[2] Application Specific Integrated Circuits , Michael John Sebastian Smith , Pearson

[3] https://www.slideshare.net/yayavaram/introduction-to-asicsntro-asi-cs
assessed on July ,2020

[4] VLSI Design and EDA Tools, Angsuman Sarkar, Swapnadip De, C.K. Sarkar, SciTech

[5] https://www.eetimes.com/all-about-fpgas/# assessed on July ,2020

Thank You