DIGITAL LOGIC DESIGN (DLD) EEE241

Chapter 5: Sequential Logic-1

Lecture 19
Dr. Nadia Nawaz

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 1

Reference
Readings and
Chapter 5: Digital Design with Introduction to
Verilog HDL M. Morris Mano, Michael D.
Acknowledge Ciletti, 5th Edition
ments

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 2

  Introduction
Lecture Sequential Circuits
Contents Synchronous sequential Circuits
 Latches and flip-flops
 SR latch
 D latch

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 3

5.1 Introduction
 Combinational circuits
◦ contains no memory elements i-e. dependence on past values of their inputs
◦ the outputs depends on the inputs
◦ Adders, subtractors, Multipliers, Encoders, Decoders, Multiplexers, Demultipexers are some of
the prime examples.

4
Sequential Circuits
◦ acts as storage elements and have memory (store, retain and then retrieve information when
needed)
◦ feedback path
◦ The binary information stored in these memory elements define the state of the sequential circuit a
that time
◦ (inputs, current state) => (outputs, next state)
◦ A sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
◦ synchronous: the transition happens at discrete instants of time
◦ asynchronous: at any instant of time

Feedback path
5
Synchronous sequential Circuits
a master-clock generator: to generate a clock signal having the form of a periodic train of clock pulses

Clock signal = clock and clk

the clock pulses are distributed throughout the system in such a way that storage devices are affected only with the arrival of
each pulse

The clock pulses determine when computational activity will occur with in the circuit

clocked sequential circuits: most commonly used

no instability problems and timing can be easily broken down into independent discrete steps

the memory elements: flip-flops

• binary cells(storage devices) capable of storing one bit of information
• two outputs: one for the normal value and one for the complement value in stable state
• maintain a binary state indefinitely until directed by an input signal to switch states

6
 Fig. 5.2
Synchronous clocked
sequential circuit

7
Latches and Flip Flops
o A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by a input signal to switch states.
o differences among various types of storage elements is based on no: of inputs and the way
inputs affects the binary state
o Latches: operate with signal levels (rather than signal transitions)
• level sensitive devices
o Flip-flops: controlled by a clock transition
• Edge-sensitive devices
o Latches are basic circuits from which all flip-flops are constructed

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 8

 Latches
SR Latch circuit
◦ two cross-coupled NOR gates or can be two cross-coupled NAND gates
◦ more complicated types can be built upon it
◦ an asynchronous sequential circuit
◦ (S,R)= (0,0): no operation
  (S,R)=(0,1): reset (Q=0, the clear state)
  (S,R)=(1,0): set (Q=1, the set state)
  (S,R)=(1,1): indeterminate state (Q=Q'=0)
◦ consider (S,R) = (1,1) Þ (0,0)

8
SR latch with NAND
gates

Fig 5.4. SR latch

with NAND gates

9
 SR Latch with Control
input
SR latch with control input
◦ En=0, no change
◦ En=1, output depends inputs S, R
S= S'

0/1

R= R'

Fig. 5.5
SR latch with control input
10
D Latch
◦ eliminate the undesirable conditions of the indeterminate state in the RS flip-flop
◦ D: data
◦ gated D-latch
◦ D Þ Q when En=1; no change when En=0

S= 1/D'

0/1

R= 1/D

Fig. 5.6 D latch

11
 Fig. 5.7
Graphic symbols for latches
12
DIGITAL LOGIC DESIGN (DLD) EEE241

Chapter 5: Sequential Logic-2

Lecture 20
Dr. Nadia Nawaz

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 14

Reference
Readings and
Chapter 5: Digital Design with Introduction to
Verilog HDL M. Morris Mano, Michael D.
Acknowledge Ciletti, 5th Edition
ments

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 15

  Flip Flops
Lecture  SR Flip Flop
Contents  D Flip Flop
 Jk Flip Flop
 T Flip Flop

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 16

 Flip-Flops
 A trigger
o The state of a latch or flip-flop is
switched by a change of the
control input
 Level triggered – latches
 Edge triggered – flip-flops

Fig. 5.8 Clock response in latch and flip-flop

4
 If level-triggered flip-flops are used
◦ the feedback path may cause instability problem
 Edge-triggered flip-flops
◦ the state transition happens only at the edge
◦ eliminate the multiple-transition problem
5
Edge-triggered D flip-flop
Master-slave D flip-flop
◦ two separate flip-flops
◦ a master flip-flop (positive-level triggered)
◦ a slave flip-flop (negative-level triggered)

Fig. 5.9 Master-slave D flip-flop

6
 CP = 1: (S,R) Þ (Y,Y'); (Q,Q') holds
 CP = 0: (Y,Y') holds; (Y,Y') Þ (Q,Q')
 (S,R) could not affect (Q,Q') directly
 the state changes coincide with the negative-edge
transition of CP

7
  Edge-triggered flip-flops
◦ the state changes during a clock-pulse transition
 A D-type positive-edge-triggered flip-flop

Fig. 5.10
D-type positive-edge-triggered flip-flop

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DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 22
 Recall D-latch

◦ three basic flip-flops

◦ (S,R) = (0,1): Q = 1 Set state
◦ (S,R) = (1,0): Q = 0 Reset state
◦ (S,R) = (1,1): no operation
◦ (S,R) = (0,0): should be avoided

Fig. 5.10
D-type positive-edge-triggered flip-flop

9
No operation No operation

Q=0 (reset) Q=0 (set)

10
 The setup time
◦ D input must be maintained at a
constant value prior to the
application of the positive CP
pulse

 The hold time

◦ D input must not changes after 50% VH 50% VH
the application of the positive CP
pulse
50% VH 50% VH
 The propagation delay time
◦ The interval between the trigger
edge and the stabilization of the
output to a new state

11
Summary
◦ CP=0: (S,R) = (1,1), no state change
◦ CP=: state change once
◦ CP=1: state holds

12
Other Flip-Flops
 The edge-triggered D flip-flops
◦ The most economical and efficient
◦ Positive-edge and negative-edge

Fig. 5.11 Graphic symbols for edge-triggered D flip-flop

13
JK flip-flop
 D=JQ'+K'Q
oJ=0, K=0: D=Q, no change
oJ=0, K=1: D=0 , Q =0 (reset)
oJ=1, K=0: D=1 , Q =1 (set)
oJ=1, K=1: D=Q’ , Q =Q'

14
TFig.
flip-flop
5.13
T flip-flop
 D = T⊕Q = TQ'+T'Q
oT=0: D=Q, no change
oT=1: D=Q’ , Q=Q'

15
Characteristic
tables

16
Characteristic equations
 D flip-flop
 Q(t+1) = D
 JK flip-flop
 Q(t+1) = JQ'+K'Q
 T flop-flop
 Q(t+1) = T⊕Q=TQ’+T’Q

17
 Direct inputs
 asynchronous set and/or asynchronous reset

Fig. 5.14 D flip-

flop with
asynchronous
reset

18
DIGITAL LOGIC DESIGN (DLD) EEE241

Chapter 5: Sequential Logic-3

Lecture 21
Dr. Nadia Nawaz

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 33

Reference
Readings and
Chapter 5: Digital Design with Introduction to
Verilog HDL M. Morris Mano, Michael D.
Acknowledge Ciletti, 5th Edition
ments

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 34

  Analysis of Clocked Sequential Ckts
 State Equation
Lecture  State Table
Contents  State Diagram

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 35

5-5 Analysis of Clocked Sequential Ckts
A sequential circuit
◦ (inputs, current state) Þ (output, next state)
◦ a state transition table or state transition diagram

Fig. 5.15
Example of sequential circuit

5-36
 State equations
Ax
 The behaviour of a clocked sequential circuit can be described
Ax+Bx Ax+Bx
algebraically by means of state equation.
Bx
 State Equation transition equation
 specifies the next state as a function of the present state and inputs
 A(t+1) = A(t)x(t) + B(t)x(t)
 B(t+1) = A'(t)x(t)

A compact form A’x

A’x
 A(t+1) = Ax + Bx
 B(t+1) = A’x

The output equation

 y(t) = (A(t)+B(t))x'(t) A+B
 y = (A+B)x' (A+B)x’

x’

5-37
State table
The time sequence of inputs, outputs and
flip-flop can be enumerated in a state table
State transition table
◦ = state equations
 A(t+1) = Ax + Bx
 B(t+1) = A’x
 y = (A+B)x‘
 A sequential circuit with m flip-flops and n
inputs needs 2m+n rows in the state table.

5-38
State equation
A(t + 1) =Ax + Bx
B(t + 1) = Ax
y = Ax + Bx

5-39
State diagram
State transition diagram
◦ a circle: a state
◦ a directed lines connecting the circles: the (clock-
triggered) transitions between the states
◦ Each directed line is labeled 'inputs/outputs‘
◦ logic diagram Û equations Û a state table Û a state
diagram

Fig. 5.16
State diagram of the circuit of Fig. 5.15

5-40
Flip-flop input equations
The part of circuit that generates the inputs to flip-flops
◦ Also called excitation functions
◦ DA = Ax +Bx
◦ DB = A'x

The output equations

◦ to fully describe the sequential circuit
◦ y = (A+B)x'

5-41
 Analysis with D flip-flops
The input equation
◦ DA=A⊕x⊕y
The state equation
◦ A(t+1)=A⊕x⊕y

Fig. 5.17
Sequential circuit with D flip-flop

5-42
DIGITAL LOGIC DESIGN (DLD) EEE241

Chapter 5: Sequential Logic-4

Lecture 22
Dr. Nadia Nawaz

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 43

Reference
Readings and
Chapter 5: Digital Design with Introduction to
Verilog HDL M. Morris Mano, Michael D.
Acknowledge Ciletti, 5th Edition
ments

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 44

 Analysis JK and T Flip-Flops
Mealy and Moore Models of FSM
Lecture
Contents

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 45

Analysis with JK flip-flops
◦ Determine the flip-flop input function in
terms of the present state and input
variables
◦ Used the corresponding flip-flop
characteristic table to determine the
next state

Fig. 5.18
Sequential circuit with JK flip-flop
5-46
 ◦ JA = B, KA= Bx'
◦ JB = x', KB = A'x + Ax‘
◦ derive the state table
◦ Or, derive the state equations
using characteristic eq.
JK flip-flop characteristic Equation
Q(t+1) = JQ'+K'Q
A(t  1)  JA  K A
B (t  1)  JB  K B
A(t  1)  BA  ( Bx) A  AB  AB  Ax
B(t  1)  xB  ( A  x )B  Bx  ABx  ABx
5-47
State transition diagram
A(t  1)  JA  K A
B (t  1)  JB  K B
State equation for A and B:

JA = B, KA= Bx'
JB = x', KB = A'x + Ax‘

A(t  1)  BA  ( Bx) A  AB  AB  Ax

B(t  1)  xB  ( A  x )B  Bx  ABx  ABx Fig. 5.19

State diagram of the circuit of Fig. 5.18
5-48
Analysis with
T flip-flops
The characteristic equation
◦ Q(t+1)= T⊕Q = TQ'+T'Q

Fig. 5.20
Sequential circuit with T flip-flop

5-49
State Table
The input and output functions
◦ TA=Bx
◦ TB= x
◦ y = AB

The state equations

◦ A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx
◦ B(t+1) = x⊕B

5-50
Mealy and Moore models
the Mealy model: the outputs are functions of both the present state and inputs
(Fig. 5-15)
◦ the outputs may change if the inputs change during the clock pulse period
◦ the outputs may have momentary false values unless the inputs are synchronized with the clocks

The Moore model: the outputs are functions of the present state only (Fig. 5-20)
◦ The outputs are synchronous with the clocks

5-51
Fig. 5.21
Block diagram of Mealy and Moore state machine
5-52
Example of Mealy Model
Clocked D-flip-flop

Fig. 5.15
Example of sequential circuit

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 53

Example of
Moore Model

Fig. 5.20
Sequential circuit with T flip-flop

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 54