Revolutionising B.

Tech
 Module 3: Computer
Arithmetic and Processing
Unit
Course Name: Computer Architecture and organization[22CSE104]
Total Hours : 8
Table of Content

• Aim
• Objective
• Computer Arithmetic
•  Introduction
•  Addition and Subtraction
•  Multiplication Algorithms
•  Division Algorithms
•  Floating-point Arithmetic operations
•  Decimal Arithmetic Unit
•  Decimal Arithmetic operations
• Processing Unit
• Instruction Codes
• Computer Registers
• Computer Instructions
• Instruction Cycle
• Addressing modes
• Data Transfer and manipulations
• RISC, CISC
Table of Content
• Self Assessments
• Activities
• Did You Know
• Summary
• Terminal Questions
Aim

To equip students in the fundamentals and understanding the

Concepts of Computer Arithmetic and Processing units
 a. Discuss on the Data arithmetic operations and hardware..
b. Understanding different Instruction codes and addressing modes.,
c. Understanding the Concept of RISC and CISC.

Objective
Introduction

• Arithmetic instructions in digital computers manipulate data to produce results

necessary for the solutions of computational problems. These instructions perform
arithmetic calculations and are responsible for the bulk of activity involved in
processing data in a computer.
• The four basic arithmetic operations are addition,subtraction,multiplication and
division.
• From these four basic operations , it is possible to formulate other arithmetic
functions and solve problems by means of numerical analysis methods.
• An arithmetic processor is the pat of a processor unit that executes arithmetic
operations.
• An arithmetic instruction may specify binary or decimal data, and in each case the
data may be in fixed-point or floating point form
• .Negative numbers may be in signed magnitude or signed compliment representation.
• Fixed point numbers may represents integers or fractions
 Addition and subtraction

The addition and subtraction algorithm for data represented in signed magnitude
and again data represented in signed-2’s complement. It is important to realize that
the adopted representation for negative numbers refers to the representation of
numbers in the register before and after the execution of the arithmetic operations.

Addition and Subtraction with Signed-magnitude Data:

The representation of numbers in signed-magnitude is familiar because it is used in

everyday arithmetic calculation. The procedure for adding or subtracting two signed
binary numbers with paper and pencils simple and straight-forward. A review of this
procedure will be helpful for deriving the hardware algorithm.
Contd..
• We designated the magnitude of the two numbers by A and B. when the signed numbers are added
or subtracted, we find that there are eight different conditions to consider, depending on the sign of
the numbers and the operation performed. These conditions are listed in the first column of the
table below.

• The other column in the table show the actual operation to be performed with the magnitude of the
numbers. The last column is needed to prevent negative zero. In other words ,when two equal
numbers are subtracted, the result should be +0 not -0. The algorithms for addition and subtraction
are derived from the table and can be stated as follows (the words inside parentheses should be
used for the subtraction algorithm) Addition (subtraction) algorithm: when the signs of A and B
are identical (different), add the two magnitude and attach the sign of A to the result. When the
sign of A and B are different (identical),compare the magnitudes
Hardware implementation
• To implement the two arithmetic operations with hardware,it is first necessary that the two
numbers be stored in registers. Let A and B be two registers that hold the magnitude of the
numbers, and As and Bs be two flipflops that hold the corresponding signs. The results of the
operation may be transferred to a third register however, a saving achieved if the result is
transferred into A and As . thus A and As together from an accumulator register.

• Consider now the hardware implementation of the algorithms above. First, a parallel adder is
needed to perform the micro operation A+B. second, comparator circuit is needed to establish if
A>B, A=B, or A
The output carry is transferred to flip-flop E. The complementer consists of
exclusive-OR gates and the parallel adder consists of full adder circuit.
Hardware algorithm
• The two signs As and Bs are compared by an exclusive-OR gate . For an add operation, identical
signs dictate that the magnitudes be added, for subtract operation different signs dictate that the
magnitudes be added. The magnitudes are added with a micro operation E A<-A+B.. Where E A is
a register that combines E and A .

• For A 0 indicates that A<B, for this case it is necessary to take the 2’s compliment of the value in A
.this operation can be done with one micro operation A<-Ā+1.
• However , we assume that A register as circuits for micro operation compliment and increment, so
the 2’s compliment is obtain from these two micro operations…
• The value in AVF provides an overflow indication. The final value of E is immaterial.
Addition and Subtraction with signed 2’s complement data
• The left most bit of binary number represents the sign bit; 0 for positive and 1 for negative. If the
sign bit is 1, the entire the entire number is represented in 2’s compliment form.
• The addition of two numbers in signed-2’s complement form consists of adding the number with
the sign bits treated the same as the other bits of the number . A carry out of the sign bit position is
discarded .
• The subtraction consists of first taking the 2’s compliment of the subtrahend and then adding it to
the minuend
• When two numbers of n digits each are added and the sum occupies n+1 Digits, we say that an
overflow occurred.
• When the two carries are applied to an exclusive-OR gate, the overflow is detected when the
output of the gate is equal to 1.
 The left most bit in AC and BR represents the sign bits of the numbers
 The over flow flip-flops V is set to 1 if there is an overflow. The output carry in this case is
discarded.
The sum is obtained by adding the contents of AC and
BR(including their sign bits). The overflow bit V is set to 1 if
the ex-OR of the last two carries is 1,and it is cleared to 0
otherwise.
Multiplication algorithms:-
• multiplication of two fixed point binary numbers in signed magnitude representation is done with
paper and pencil of successive shift and add operation .

if the multiplier bit is a 1,the multiplicand is copied down;

otherwise zero are copied down.
Hardware Implementation for Signed-Magnitude data
•  When multiplication is implemented in a digital computer, it is convenient to change the process
slightly. First instead of providing register to store and add simultaneously as many binary
numbers as there are bits in the multiplier , as it is convenient to provide an adder for the
summation of only two binary numbers and successively accumulate the partial products in a
register. Second instead of shifting the multiplicand to the left , the partial product is shifted to the
right
•  The hardware for multiplication consists of the equipment shown in fig. plus two are more
registers.
•  These registers are together with registers A and B..
•  The multiplier stored in the Q register and its sign in Qs The sequence counter SC is initially set
to a number equal to the number of bits in the multiplier. The counter is decremented by 1 after
forming each partial product
•  The sum of A and B forms a partial product which is transferred to the EA register .
The shift will be denoted by the statement shr EAQ to designate
the right shift depicted . The least significant bit of A is shifted
into the most significant position of Q.
Hardware Algorithm
• Below fig.is a flowchart of the hardware multiply algorithm.. Initially the multiplicand is in B and
the multiplier in Q there corresponding signs are in Bs and Qs .,respectively.
• Register A and E are cleared and the sequence counter SG is set to a number equal to the number
of bits of the multiplier.
• After the initialization , the low order bit of the multiplier is in Qn is tested .if it is 1,the
multiplicand In B is added to the present partial product in A . If it is 0, nothing is done .
• Register EAQ shifted once to the right to form the new partial product.
• The process stops when SC=0.
• Note that the partial product formed in A is shifted into Q one bit at a time and eventually replaces
multiplier.
• The final product is available in both A and Q,with A holding the most significant bits and Q
holding the least significant bits.
Booth Multiplication Algorithm
• Booth Algorithm gives a procedure for multiplying binary integers in signed-2’s compliment representation .
Hardware for booth algorithm
• The algorithm requires the register configuration as shown in fig.
Booth algorithm for multiplication of signed-2’s compliment
• The two bits of multiplier in Qn and Qn+1 are
inspected . If the two bits are equal to 10 it
means that the first 1 in a string of 1’s has been
encountered .
• The final value of Qn+1 is the original sign bit
of the multiplier and should not be taken as
part of the product .
Array multiplier
• The multiplication of the two binary numbers can be done with one micro-operation by means of a
combinational circuit that forms the product bits all at once. This is a fast way of multiplying two
numbers since all it takes is the time for the signals to propagate through the gate that form the
multiplication array.
Division Algorithm
•  Division of two fixed-point binary numbers in signed magnitude representation is done with
paper and pencil by a process of successive compare ,shift ,and subtract operations ..
• Hardware implantation of signed magnitude data
Example of binary division with digital hardware
• Instead of shifting the divisor to the right, the
dividend or partial remainder, is shifted to the left,
thus leaving the two numbers in the required
relative position, subtraction may be achieved by
adding A to the 2’s compliment of B.
• EAQ is shifted to the left with 0 instead of Qn and
the previous value of E lost.
• The divisor is stored in the B register and the
double length dividend is stored in register A and Q
The information about relative magnitude is
available in E. if E=1,it signifies that A ≥B.
• A quotient bit 1 is inserted into Qn and the partial
remainder is shifted left to repeat the process. If
E=0, it signifies that A<B so the quotient in Qn
remains a 0.
• The sign of the remainder is the same as the sign of
the dividend
Divide overflow
•  This occurs because any dividend will be greater than or equal to zero.
•  Over flow condition is usually detected when a special flip-flop is set . Which will call it a
divide overflow flip-flop and label it DVF
•  The occurrence of a divide overflow can be handled in variety of ways
•  In some computers it is the responsibility of the programmers to check if DVF is set after each
divide instruction
•  The occurrence of a divide overflow stopped the computer and this condition was referred to as
a DIVIDE STOP.
•  The best way to avoid a divide overflow is to use floating point data
•  The divide overflow can be handled very simply if numbers are in floating point representation.
 Hardware algorithm

• The dividend is in A and Q and the divisor in

B. The sign of the results transferred into Qs
to be part of quotient.
• A divide overflow condition is tested by
subtracting divisor in B from half of the bits
of the dividend stored in A. if A≥B, the
divide overflow flip-flop DVF set and the
operation is terminated prematurely.
• By doing the process as shown in the
flowchart the quotient magnitude is formed
in register Q and the remainder is found in
the register A. The quotient sign is in Qs and
the sign of the remainder in As is the same as
the original sign of the dividend.
What is restoring method?
• The hardware method just described is called the RESTORING METHOD. The reason for the
name is that the partial remainder is restored by adding the divisor to the negative difference. Two
other methods are available for dividing numbers, the COMPARISION method and the
NONRESTORING method. In the comparison method A and B are compared prior to the
subtraction operation .

•  No restoring method B is not added if the difference is negative but instead, the negative
difference is shifted left and then B is added.
Floating point Arithmetic operation
•  Floating point number in computer register consists of two parts: a mantissa m and exponent e
--------> m X r^e
•  A floating point number that has a 0 in the most significant position of the mantissa is said to
have an UNDERFLOW. To normalize a number that contains an underflow, it is necessary to shift
the mantissa to the left and decrement the exponent until a nonzero digit appears in the first
position.

Register configuration

The register configuration for floating point operation is quite similar to the layout for fixed point
operation. As a general rule, the same register and adder used for fixed point arithmetic are used for
processing the mantissas. The difference lies in the way the exponents are handled.
Register organization
• There are three registers, BR,
AC,and QR. Each register is
subdivided into two parts. The
mantissa part has same upper
case letters, the exponent part
uses the corresponding lower
case letters.
• A parallel adder adds the two
mantissas and transfers the sum
into A and the carry into E. A
separate parallel adder is used
for the exponents. Since the
exponents are biased.
Addition and subtraction
• During addition and subtraction , the two floating point operands are in AC and BR. The sum of
difference is formed in the AC . The algorithm can be divided into four consecutive parts :
• 1. Check for zeros.
• 2. Align the mantissa.
• 3. Add or subtract the mantissa.
• 4. Normalize the result.
Multiplication
•  The multiplication of two floating point numbers requires that we multiply the mantissas and
add the exponents. No comparison of exponents or alignment of mantissa is necessary.
•  The multiplication of the mantissa is performed same as fixed point to provide a double
precision product.
•  The multiplication algorithm can be subdivided into four parts :-
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissa.
4. Normalize the product.
Division
• Floating point division requires that the exponents be subtracted and the mantissa divided. The
mantissa division is done as in fixed point except that the dividend has a single precision mantissa
that is placed in the AC.
•  The division algorithm can be divided into five parts..
1. Check for zeros.
2. Initialize registers and evaluate the sign.
3. Align the dividend
4. Subtract the exponents.
5. Divide the mantissa.
BCD Adder
BCD Subtraction
• A straight subtraction of two decimal numbers will require a subtractor circuit that will be
somewhat different from a BCD adder.
•  It is more economical to perform the subtraction by taking the 9’s or 10’s complement of the
subtrahend and adding it to the minuend. Since the BCD is not a self-complementing code
•  The Boolean functions for the 9’s complement circuit are
• x1 = B1M’+B1’M
• x2 = B2
• x4 = B4M’ + (B4’B2 + B4B2’)M
• x8 = B8M’ + B8’B4’B2’M
from these equations we see that x=B when M=0. when M=1,the x output produce the 9’s
compliment of B
Decimal Arithmetic operation
• The algorithms for arithmetic operations with decimal data are similar to the algorithms for the
corresponding operations with binary data.
Decimal arithmetic micro operation symbols
Addition and Subtraction
Processing Unit
Instructions Codes
• What is Instruction code
• Instruction codes are bits that instruct the computer to execute a specific operation. An instruction
comprises groups called fields. These fields include:
• An instruction comprises groups called fields. These fields include:
• The Operation code (Opcode) field determines the process that needs to perform.
• The Address field contains the operand's location, i.e., register or memory location.
• The Mode field specifies how the operand locates.
• Instruction Format
• Structure of an Instruction Code
• The instruction code is also known as an instruction set. It is a collection of binary codes. It represents the operations
that a computer processor can perform. The structure of an instruction code can vary. It depends on the architecture
of the processor but generally consists of the following parts:
• Opcode: The opcode (Operation code) represents the operation that the processor must perform. It might indicate
that the instruction is an arithmetic operation such as addition, subtraction, multiplication, or division.
 
• Operand(s): The operand(s) represents the data that the operation must be performed on. This data can take various
forms, depending on the processor's architecture. It might be a register containing a value, a memory address
pointing to a location in memory where the data is stored, or a constant value embedded within the instruction itself.
 
• Addressing mode: The addressing mode represents how the operand(s) can be interpreted. It might indicate that the
operand is a direct address in memory, an indirect address (i.e. a memory address stored in a register), or an
immediate value (i.e. a constant embedded within the instruction).
 
• Prefixes or modifiers: Some instruction sets may include additional prefixes or modifiers that modify the behavior
of the instruction. For example, they may specify that the operation should be performed only if a specific condition
is met or that the instruction should be executed repeatedly until a specific condition is met.
Types of Instruction Code

• There are various types of instruction codes. They are classified based on the number of operands, the type
of operation performed, and the addressing modes used. The following are some common types of
instruction codes:
• One-operand instructions: These instructions have one operand and perform an operation on that operand.
For example, the "neg" instruction in the x86 assembly language negates the value of a single operand.
 
• Two-operand instructions: These instructions have two operands and perform an operation involving both.
For example, the "add" instruction in x86 assembly language adds two operands together.
 
• Three-operand instructions: These instructions have three operands and perform an operation that involves
all three operands. For example, the "fma" (fused multiply-add) instruction in some processors multiplies
two operands together, adds a third operand, and stores the result in a fourth operand.
 
• Data transfer instructions: These instructions move data between memory and registers or between
registers. For example, the "mov" instruction in the x86 assembly language moves data from one location to
another.
 
• Control transfer instructions: These instructions change the flow of program execution by modifying the
program counter. For example, the "jmp" instruction in the x86 assembly language jumps to a different
location in the program.
 
• Arithmetic instructions: These instructions perform mathematical operations on operands. For example,
the "add" instruction in x86 assembly language adds two operands together.
 
• Logical instructions: These instructions perform logical operations on operands. For example, the "and"
instruction in x86 assembly language performs a bitwise AND operation on two operands.
 
• Comparison instructions: These instructions compare two operands and set a flag based on the result. For
example, the "cmp" instruction in x86 assembly language compares two operands and sets a flag indicating
whether they are equal, greater than, or less than.
 
• Floating-point instructions: These instructions perform arithmetic and other operations on floating-point
numbers. For example, the "fadd" instruction in the x86 assembly language adds two floating-point
numbers together.
Opcodes

• An opcode is a collection of bits representing the basic operations, including add, subtract,
multiply, complement, and shift. The number of bits required for the opcode is determined by the
number of functions the computer gives. For ‘2n’ operations, the minimum bits accessible to the
opcode should be ‘n’, where n is the number of bits. We implement these operations on
information saved in processor registers or memory.
Types of Opcodes

• There are three different types of instruction codes on the main computer. The instruction's
operation code (opcode) is 3 bits long, and the remaining 13 bits are determined by the operation
code encountered.
• There are three types of formats:
• Memory Reference Instruction: It specifies the address with 12 bits and the addressing mode with
1 bit (I). For direct addresses, I equal 0, while for indirect addresses, I equal 1.
• Register Reference Instruction: The opcode 111 with a 0 in the leftmost bit of the instruction
recognizes these instructions. The remaining 12 bits specify the procedure to be carried out.
• Input-Output Instruction: The operation code 111 with a 1 in the leftmost bit of instruction
recognizes these instructions. The input-output action is specified using the remaining 12 bits.
Address

• We represent the memory address where a given instruction is built. We use an instruction code's
address bits as an operand rather than an address. The instruction in such methods has an
immediate operand. The command is directed to a direct address if the second portion contains an
address.
• In the second half, there is another choice, which includes the operand's address. It points to an
oblique address. One bit might indicate whether the instruction code executes the direct or indirect
address.
• Addressing Modes
• We can mainly describe the address field for instruction in the following ways:
• Direct Addressing − Uses the address of the operand.
• Indirect Addressing − Enables the address as a pointer to the operand.
• Immediate operand − The second part of the instruction code specifies an operand. 
• Accumulator Register (AC): This register is found in single register processors (AC), and it
performs all operations with memory operands.
• Effective Address (EA) is the address of the operand or the target address. It defines the address
that we can execute as a target address for a branch-type instruction or the address we can use
directly to create an operand for a computation-type instruction without any changes.
Types of Addressing Modes

• We have discussed below the different types of addressing modes:

• Immediate Mode
• An immediate mode instruction specifies the operand in the instruction itself rather than the
address field. For example, the expression “ADD 100” adds 100 to the contents of the
accumulator. 100 here is the operand.
• Register Mode
• We store operands in the register in the CPU, and instruction addresses are the addresses of the
registers in which operands are stored.
• Advantages of Addressing Modes  • Register Indirect Mode
• Shorter instructions and faster instruction fetch.
• Speedier memory access to the operand(s).
• Disadvantages of Addressing Modes
• Minimal address space.
• Using multiple registers allows performance,
but it complicates the instructions
• Register Indirect Mode
• A register that specifies the address of an
operand located in memory is used in this
mode. Thus, the register possesses the address
of the operand rather than the operand itself.
• Auto Increment/Decrement Mode
• The register increments or decrements after or before it uses the value.
• Direct Addressing Mode
• In this, we include the operand's effective address in the instruction.
• Data is accessed using a single memory reference.
• There are no extra calculations required to determine the operand's effective address.
• Indirect Addressing Mode
• The address component of the instruction defines where the effective address is stored in memory
because several memory lookups are required to locate the operand, slowing down the execution.
• Displacement Addressing Mode
• To acquire the effective address of the operand, we append the contents of the indexed register to
the Address section of the instruction.
• EA = A + (R), where the address field contains two values: A (the base value) and R (the
Displacement), or vice versa.
• Relative Addressing Mode
• It's a Displacement addressing mode variant. PC (Program Counter) contents are added to the
instruction's address component to acquire the effective address.
• EA = A + (PC), where PC is the program counter, and EA is the effective address.
• A cell apart from the current cell is the operand (the one pointed to by PC).
• Base Register Addressing Mode
• It's a variation of Displacement addressing mode. 
• EA = A + (R), where A is the displacement and R is the pointer to the base address.
What are Computer Registers in Computer Architecture?

• Computer registers are high-speed memory storing units. It is an element of the computer
processor. It can carry any type of information including a bit sequence or single data.
• A register should be 32 bits in length for a 32-bit instruction computer. Registers can be numbered
relies upon the processor design and language rules.
• The instructions in a computer are saved in memory locations and implemented one after another
at a time. The function of the control unit is to fetch the instruction from the memory and
implement it. The control does the similar for all the instructions in the memory in sequential
order.
• A counter is needed to maintain a path of the next instruction to be implemented and evaluate its
address. The figure shows the registers with their memories. The memory addresses are saved in
multiple registers. These requirements certainly state the use for registers in a computer.
The description for each of the registers determined in the figure is as follows −

• The data register holds the operand read from the memory.
• The accumulator is a general-purpose register need for processing.
• The instruction register holds the read memory.
• The temporary data used while processing is stored in the temporary register.
• The address register holds the address of the instruction that is to be implemented next from the
memory.
• The Program Counter (PC) controls the sequence of instructions to be read. In case a branch
instruction is detected, the sequential execution does not arise. A branch execution calls for a
transfer to an instruction that is not in sequence with the instructions in the PC.
• The input register (INPR) and output register (OUTPR) are the registers used for the I/O
operations. The INPR receives an 8-bit character from the input device. It is similar to the OUTPR
What are Computer Instructions?

• A computer has programs stored in its RAM in the form of 1s and 0s that are interpreted by the
CPU as instructions. One word of RAM includes one instruction in the machine language.
• These instructions are loaded to the CPU one at a time, where it receives decoded and
implemented. A basic computer has three instruction code formats such as the memory reference
instruction, the register reference instruction, and the input-output instruction format.
Memory Reference Instruction
• A memory-reference instruction uses 12 bits to specify an address and one bit to determine the
addressing mode I. I is the same as 0 for direct address and to 1 for indirect address.
Register Reference Instruction
• The register reference instructions are identified by the operation code 111 with a 0 in the leftmost
bit (bit 15) of the instruction. It determines an operation on or a test of the AC register. An operand
from memory is not required because the additional 12 bits are used to determine the operation or
test to be implemented.

Input-Output Instruction
An input-output instruction does not require a reference to memory and is identified by the operation code 111
with a 1 in the leftmost bit of the instruction. The remaining 12 bits can determine the type of input-output
operation or test implemented.
• The type of instruction is identified by the computer control from the four bits in positions 12
through 15 of the instruction. If the three opcode bits in positions 12 through 14 are not similar to
111, the instruction is a memory-reference type and the bit in position 15 is taken as the addressing
mode I.
• If the 3-bit opcode is similar to 111, the control then examines the bit in position 15. If this bit is 0,
the instruction is a register-reference type. If the bit is 1, the instruction is an input-output type.
Instruction Cycle

• A program residing in the memory unit of a computer consists of a sequence of instructions. These
instructions are executed by the processor by going through a cycle for each instruction.
• In a basic computer, each instruction cycle consists of the following phases:
• Fetch instruction from memory.
• Decode the instruction.
• Read the effective address from memory.
• Execute the instruction.
• After the following four procedures are done, the control switches back to the first step and repeats
the similar process for the next instruction. Therefore, the cycle continues until a Halt condition is
met. The figure shows the phases contained in the instruction cycle.
Fetch Cycle
• The address instruction to be implemented is held at the program counter. The processor fetches
the instruction from the memory that is pointed by the PC.
• Next, the PC is incremented to display the address of the next instruction. This instruction is
loaded onto the instruction register. The processor reads the instruction and executes the important
procedures.
Execute Cycle
• The data transfer for implementation takes place in two methods are as follows −
• Processor-memory − The data sent from the processor to memory or from memory to processor.
• Processor-Input/Output − The data can be transferred to or from a peripheral device by the
transfer between a processor and an I/O device.
• In the execute cycle, the processor implements the important operations on the information, and
consistently the control calls for the modification in the sequence of data implementation. These
two methods associate and complete the execute cycle.
State Diagram for Instruction Cycle

• The figure provides a large aspect of the instruction cycle of a basic computer, which is in the
design of a state diagram. For an instruction cycle, various states can be null, while others can be
visited more than once.
• Instruction Address Calculation − The address of the next instruction is computed. A permanent
number is inserted to the address of the earlier instruction.
• Instruction Fetch − The instruction is read from its specific memory location to the processor.
• Instruction Operation Decoding − The instruction is interpreted and the type of operation to be
implemented and the operand(s) to be used are decided.
• Operand Address Calculation − The address of the operand is evaluated if it has a reference to
an operand in memory or is applicable through the Input/Output.
• Operand Fetch − The operand is read from the memory or the I/O.
• Data Operation − The actual operation that the instruction contains is executed.
• Store Operands − It can store the result acquired in the memory or transfer it to the I/O.
Data Manipulation Instructions :
• Data manipulation instructions perform operations on data and provide the computational
capabilities for the computer. The data manipulation instructions in a typical computer usually
divided into three basic types as follows.
• Arithmetic instructions
• Logical and bit manipulation instructions
• Shift instructions
• Data Transfer Instructions
Arithmetic instructions :
The four basic arithmetic operations are addition, subtraction, multiplication, and division. Most
computers provide instructions for all four operations. Typical Arithmetic Instructions –
Name Mnemonic Example Explanation

Increment INC INC B It will increment the register B by 1 B<-B+1

Decrement DEC DEC B It will decrement the register B by 1 B<-B-1

Add ADD ADD B It will add contents of register B to the contents of the accumulator and store the result in the accumulator AC<-AC+B

Subtract SUB SUB B It will subtract the contents of register B from the contents of the accumulator and store the result in the accumulatorAC<-AC-B

Multiply MUL MUL B It will multiply the contents of register B with the contents of the accumulator and store the result in the accumulator AC<-AC*B

Divide DIV DIV B It will divide the contents of register B with the contents of the accumulator and store the quotient in the accumulator AC<-AC/B

Add with carry ADDC ADDC B It will add the contents of register B and the carry flag with the contents of the accumulator and store the result in the accumulator AC<-
AC+B+Carry flag

Subtract with borrow SUBB SUBB B It will subtract the contents of register B and the carry flag from the contents of the accumulator and store the result in the accumulator AC<-AC-
B-Carry flag

Negate(2’s NEG NEG B It will negate a value by finding 2’s complement of its single operand. This means simply operand by -1.B<-B’+1
complement)
• Logical instructions perform binary operations on strings of bits stored in registers. They are
useful for manipulating individual bits or a group of bits.Typical Logical and Bit Manipulation
Instructions –
 Name Mnemonic Example Explanation

Clear CLR CLR It will set the accumulator to 0 AC<-0

Complement COM COM A It will complement the accumulatorAC<-(AC)’

AND AND AND B It will AND the contents of register B with the contents of accumulator and store it in the accumulatorAC<-AC AND B

OR OR OR B It will OR the contents of register B with the contents of accumulator and store it in the accumulator AC<-AC OR B

Exclusive-OR XOR XOR B It will XOR the contents of register B with the contents of the accumulator and store it in the accumulator AC<-AC XOR B

Clear carry CLRC CLRC It will set the carry flag to 0 Carry flag<-0

Set carry SETC SETC It will set the carry flag to 1 Carry flag<-1

Complement carry COMC COMC It will complement the carry flag Carry flag<- (Carry flag)’

Enable interrupt EI EI It will enable the interrupt

Disable interrupt DI DI It will disable the interrupt

• Shift Instructions :
Shifts are operations in which the bits of a word are moved to the left or right. Shift instructions
may specify either logical shifts, arithmetic shifts, or rotate-type operations.Typical Shift
Instructions –
Data Transfer Instructions
RISC and CISC

• Reduced Instruction Set Architecture (RISC) – 

The main idea behind this is to make hardware simpler by using an instruction set composed of a
few basic steps for loading, evaluating, and storing operations just like a load command will load
data, a store command will store the data. 
• Complex Instruction Set Architecture (CISC) – 
The main idea is that a single instruction will do all loading, evaluating, and storing operations just
like a multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s
complex. 
• Both approaches try to increase the CPU performance 
• RISC: Reduce the cycles per instruction at the cost of the number of instructions per program. 
 
• CISC: The CISC approach attempts to minimize the number of instructions per program but at the
cost of an increase in the number of cycles per instruction. 
Earlier when programming was done using assembly language, a need was felt to make instruction do
more tasks because programming in assembly was tedious and error-prone due to which CISC
architecture evolved but with the uprise of high-level language dependency on assembly reduced
RISC architecture prevailed. 
• Characteristic of RISC – 
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved. 
• Characteristic of CISC – 
• Complex instruction, hence complex instruction decoding.
• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to get executed.
• Less number of general-purpose registers as operations get performed in memory itself.
• Complex Addressing Modes.
• More Data types. 
• Example – Suppose we have to add two 8-bit numbers: 
• CISC approach: There will be a single command or instruction for this like ADD which will perform the
task.
• RISC approach: Here programmer will write the first load command to load data in registers then it will
use a suitable operator and then it will store the result in the desired location.
• So, add operation is divided into parts i.e. load, operate, store due to which RISC programs are longer and
require more memory to get stored but require fewer transistors due to less complex command. 
 Did You Know?
1. There are three registers, BR, AC,and QR. Each register is subdivided into two parts. The
mantissa part has same upper case letters, the exponent part uses the corresponding lower case
letters.
2. Efficient data representation can reduce the amount of memory required to store data, and can
improve the speed at which data is processed and transmitted.
3. Additionally, understanding data representation is essential for writing efficient and error-free
code in programming languages that interact with the computer's hardware.
4. Instruction Codes contain mode, Opcode and operand.
5. To execute an Instruction it needs to follow a 4 step instruction cycle.
6. A register is a group of flip-flops used to store binary information within a digital system.
Registers are used to hold data temporarily, to enable processing, or to store data between
different operations within a system. Registers are also used to hold addresses and control
signals in microprocessors.
7. RISC: Reduce the cycles per instruction at the cost of the number of instructions per program.  
8. CISC: The CISC approach attempts to minimize the number of instructions per program but at
the cost of an increase in the number of cycles per instruction
Summary

Outcomes:
a. Discuss the theory of Floating point airthmetics.
b. Differentiate between RISC and CISC.
c. Consider a processor with 64 registers and an instruction set of size
twelve. Each instruction has five distinct fields, namely, opcode, two
source register identifiers, one destination register identifier, and a
twelve-bit immediate value. Each instruction must be stored in memory
in a byte-aligned fashion. If a program has 100 instructions, the amount
of memory (in bytes) consumed by the program text is
Terminal Questions
1) What are the different Registers? Name them.
2) What are the different Data manipulation operations.
Reference Links

• https://www.geekforgeeks.org/computer organization
Reference Material:
• M. Moris Mano, “Computer Systems Architecture”, 4th Edition, Pearson/PHI,
ISBN:10:0131755633
Thank you