VLSI Design, (KEC-072)

Unit V VLSI Testing

 VLSI Testing
As the number of transistors integrated into a single chip increases, the task of chip
testing to ensure correct functionality becomes increasingly more difficult. However, in a
production environment, many chips must be tested within a short time for timely
delivery to customers. To overcome such difficult issues, design for testability has
become ever more critical.

Input test vectors are devised and applied to the device under test (DUT) or circuit under
test (CUT) as its stimuli. Then the measured outputs are compared with the expected
correct responses to determine whether DUT is good or bad.
 Scan-Based Techniques
The controllability and observability can be enhanced by providing more accessible logic nodes with use of additional
primary input lines and multiplexors.

The use of additional I/O pins can be costly not only for chip fabrication but also for packaging. A popular alternative is to
use scan registers with both shift and parallel load capabilities.

The scan design technique is a structured approach to design sequential circuits for testability. The storage cells in registers
are used as observation points, control points, or both.

By using the scan design techniques, the testing of a sequential circuit is reduced to the problem of testing a combinational
circuit.

In general, a sequential circuit consists of a combinational circuit and some storage elements. In the scan-based design, the
storage elements are connected to form a long serial shift register, the so-called scan path, by using multiplexors and a
mode (test/ normal) control signal.

In the test mode, the scan-in signal is clocked into the scan path, and the output of the last stage latch is scanned out. In the
normal mode, the scan-in path is disabled and the circuit functions as a sequential circuit. The testing sequence is as
follows:
•Step 1: Set the mode to test and, let latches accept data from scan-in input.

•Step 2: Verify the scan path by shifting in and out the test data.

•Step 3: Scan in (shift in) the desired state vector into the shift register.

•Step 4: Apply the test pattern to the primary input pins.

•Step:5 Set the mode to normal and observe the primary outputs of the circuit after sufficient
time for propagation.
•Step:6 Assert the circuit clock, for one machine cycle to capture the outputs of the
combinational logic into the registers.
•Step 7: Return to test mode; scan out the contents of the registers, and at the same time scan
in the next pattern.
•Step 8: Repeat steps 3-7 until all test patterns are applied.
• The main idea in scan design is to obtain control and observability for flip-flops.
This is done by adding a test mode to the circuit such that when the circuit is in
this mode, all flip-flops functionally form one or more shift registers.
• The inputs and outputs of these shift registers (also known as scan registers) are
made into primary inputs and primary outputs. Thus, using the test mode, all flip-
flops can be set to any desired states by shifting those logic states into the shift
register.
• Similarly, the states of flip-flops are observed by shifting the contents of the scan
register out. All flip-flops can be set or observed in a time (in terms of clock
periods) that equals the number of flip-flops in the longest scan register
 Pseudo Random Pattern Generator
To test the circuit, test patterns first have to be generated either by
using a pseudo random pattern generator, a weighted test generator,
an adaptive test generator, or other means. A pseudo random test
generator circuit can use an LFSR.
• Signature Analysis – A method of circuit response compaction during testing,
whereby the entire good circuit response is compacted into a good machine
signature. The actual circuit signature is generated during the testing process on
the CUT, and then compared with the good machine signature to determine
whether the CUT is faulty.
• Output Response Analyzer
• The on-chip storage of a fault dictionary containing all test inputs with the
corresponding outputs is prohibitively expensive in terms of the chip area. A
simple alternative method is to compare the outputs of two identical circuits for
the same input, with one of them regarded as reference. However, if both circuits
have the same faults, their outputs can still match. Such faults cannot be detected
with this technique, although, the probability of two identical circuits having
exactly the same faults would be very low.
 Current Monitoring IDDQ Test
• An often-used technique for testing fabrication defects is the IDDQ test. Under a bridging fault,
the static currents drawn from the power supply in CMOS circuits can be noticeably high,
well beyond the expected range of leakage currents. For example, if the drain node of the
pMOS transistor in a CMOS inverter is shorted to the power supply rail due to a bridging
fault, its IDDQ current can be very high even when the input is high. It can also detect other
fabrication defects not easily detected by other test methods, including:

• Gate oxide short

• Channel punch-through

• p-n diode leakage

• Transmission-gate defect
• The design guidelines for IDDQ testability are as follows:

• Low static current states, e.g., full CMOS is preferred

• No active pull-ups or pull-downs
• No internal drive conflicts, e.g., drivers share a bus
• No floating nodes in the circuit

• No degraded voltages, e.g., must have VOH = VDD and VOL = 0

 Advantages and disadvantages

Iddq testing has many advantages:

• It is a simple and direct test that can identify physical defects.
• The area and design time overhead are very low.
• Test generation is fast.
• Test application time is fast since the vector sets are small.
• It catches some defects that other tests, particularly stuck-at logic tests, do not.
Drawback: Compared to scan chain testing, Iddq testing is time consuming, and thus more expensive,
as is achieved by current measurements that take much more time than reading digital pins in
mass production.
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