Why worry about power?

-- Power Dissipation

Lead microprocessors power continues to increase

100

P6
Pentium ®
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation will be prohibitive

Source: Borkar, De Intel
 Why worry about power? -- Chip Power Density

Sun’s
10000 Surface
Rocket
Power Density (W/cm2)

1000 Nozzle
Nuclear …chips might become hot…

100 Reactor

8086 Hot Plate

10 4004 P6
8008 8085 386 Pentium®
286 486
8080
1
1970 1980 1990 2000 2010
Year
Source: Borkar, De Intel
Chip Power Density Distribution
Power Map On-Die Temperature

 Power density is not uniformly distributed across the chip

 Silicon is not a good heat conductor
 Max junction temperature is determined by hot-spots
 Impact on packaging, w.r.t. cooling
Why worry about power ? -- Battery Size/Weight
50
Rechargable Lithium

Nominal Capacity (W-hr/lb)

40

Ni-Metal Hydride
30

20
Nickel-Cadmium
Battery
(40+ lbs) 10

0
65 70 75 80 85 90 95

Year

Expected battery lifetime increase

over the next 5 years: 30 to 40% From Rabaey, 1995
Why worry about power? -- Standby Power
Year 2002 2005 2008 2011 2014
Power supply Vdd (V) 1.5 1.2 0.9 0.7 0.6
Threshold VT (V) 0.4 0.4 0.35 0.3 0.25

 Drain leakage will increase as VT decreases to maintain noise

margins and meet frequency demands, leading to excessive
battery draining standby power consumption.
50%
8KW
…and phones leaky!
40% 1.7KW
Standby Power

30% 400W

20%
88W
12W
10%

0%

2000 2002 2004 2006 2008 Source: Borkar, De Intel

Power and Energy Figures of Merit
 Power consumption in Watts
 Average power

 Sets packaging limits

 Packaging and Cooling costs

 Peak power is the maximum instantaneous power

 Determines power ground wiring designs
 impacts signal noise margin and reliability analysis
Power and Energy Figures of Merit

 Energy efficiency in Joules

 rate at which power is consumed over time
 determines battery life

 Energy = power * delay

 Joules = Watts * seconds

 lower energy number means less power to perform a
computation at the same frequency
Power versus Energy

Power is height of curve

Watts Lower power design could simply be slower
Approach 1

Approach 2

time
Energy is area under curve
Watts Two approaches require the same energy
Approach 1

Approach 2

time
PDP and EDP
 Power-delay product (PDP) = Pav * tp = (CLVDD2)/2
 PDP is the average energy consumed per switching event
(Watts * sec = Joule)
 lower power design could simply be a slower design
 Energy-delay product (EDP) = PDP * tp = Pav * tp2
15
 EDP is the average energy
consumed multiplied by the energy-delay
computation time required
10
 takes into account that one

alized)
can trade increased delay
for lower energy/operation energy
elay(norm
(e.g., via supply voltage 5
scaling that increases delay,
nergy-D

delay
but decreases energy
consumption)
E

0
0.5 1 1.5 2 2.5
 allows one to understand tradeoffs better Vdd (V)
 Understanding Tradeoffs
 Which design is the “best” (fastest, coolest, both) ?

Lower
EDP
b
Energy
better

c a

1/Delay

better
Dynamic Power Consumption
Vdd

Vin Vout

CL

Energy/transition =1/2* CL * VDD2 * α

Pdyn = Energy/transition * f =1/2* CL * VDD2 * f *α

Pdyn = 1/2* CEFF * VDD2 * f where CEFF = α CL

Not a function of transistor sizes!
Data dependent - a function of switching activity!
Lowering Dynamic Power

Capacitance: Supply Voltage:

Function of fan-out, Has been dropping
wire length, transistor with successive
sizes generations

Pdyn = ½*CL VDD2 f α

Activity factor: Clock frequency:

How often, on average, Increasing…
do wires switch?
Short Circuit Power Consumption

Vin Isc Vout

CL

Finite slope of the input signal causes a direct

current path between VDD and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Short Circuit Currents Determinates

Esc = tsc VDD Ipeak α

Psc = tsc VDD Ipeak f α

 Duration and slope of the input signal, tsc
 Ipeak determined by
 the saturation current of the P and N transistors which
depend on their sizes, process technology, temperature, etc.
 strong function of the ratio between input and output slopes
- a function of CL
 Impact of CL on Psc

Isc  0 Isc  Imax

Vin Vout Vin Vout

CL CL

Large capacitive load Small capacitive load

Output fall time significantly Output fall time substantially

larger than input rise time. smaller than the input rise
time.
 Ipeak as a Function of CL

x 10-4
2.5
When load capacitance
2 CL = 20 fF is small, Ipeak is large.

1.5
Ipeak (A)

1 CL = 100 fF
Short circuit dissipation
0.5 is minimized by
CL = 500 fF matching the rise/fall
0 times of the input and
0 2 4 6 output signals - slope
-0.5 x 10-10

time (sec)
engineering.
500 psec input slope
 Psc as a Function of Rise/Fall Times
8
7 When load capacitance
is small (tsin/tsout > 2 for
6 VDD= 3.3 V
VDD > 2V) the power is
5
P normalized

dominated by Psc
4
3 VDD = 2.5 V
If VDD < VTn + |VTp| then
2
Psc is eliminated since
1 VDD = 1.5V both devices are never
0 on at the same time.
0 2 tsin/tsout 4
W/Lp = 1.125 m/0.25 m normalized wrt zero input
W/Ln = 0.375 m/0.25 m rise-time dissipation
CL = 30 fF
 Reverse bias current
 Weak inversion current
 DIBL

 Gate induced Drain leakage

 Punch through
 Narrow width effect
 Gate oxide tunneling
 Hot carrier injection
Leakage (Static) Power Consumption

VDD Ileakage

Vout
Drain junction
leakage

Gate leakage Sub-threshold current

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

 Leakage as a Function of VT
 Continued scaling of supply voltage and the subsequent
scaling of threshold voltage will make subthreshold
conduction a dominate component of power dissipation.

10-2
 An 90mV/decade VT
roll-off - so each
255mV increase in
VT gives 3 orders of
ID (A)

10-7 magnitude reduction

in leakage (but
VT=0.4V adversely affects
VT=0.1V performance)
10-12
0 0.2 0.4 0.6 0.8 1
VGS (V)
TSMC Processes Leakage and VT

CL018 CL018 CL018 CL018 CL015 CL013

G LP ULP HS HS HS
Vdd 1.8 V 1.8 V 1.8 V 2V 1.5 V 1.2 V
Tox (effective) 42 Å 42 Å 42 Å 42 Å 29 Å 24 Å
Lgate 0.16 m 0.16 m 0.18 m 0.13 m 0.11 m 0.08 m
IDSat (n/p) 600/260 500/180 320/130 780/360 860/370 920/400
(A/m)
Ioff (leakage) 20 1.60 0.15 300 1,800 13,000
(A/m)
VTn 0.42 V 0.63 V 0.73 V 0.40 V 0.29 V 0.25 V
FET Perf. 30 22 14 43 52 80
(GHz)

From MPR, 2000

Exponential Increase in Leakage Currents

10000

1000
0.25
Ileakage(nA/m)

0.18
100
0.13
0.1
10

1
30 40 50 60 70 80 90 100 110
Temp(C)

From De,1999
Dynamic Power as a Function of Device Size
 Device sizing affects dynamic energy consumption
 gain is largest for networks with large overall effective fan-outs (F =
CL/Cg,1)
 The optimal gate sizing factor
1.5
(f) for dynamic energy is
smaller than the one for F=1
performance, especially for

normalized energy
F=2
large F’s 1

 e.g., for F=20, F=5

fopt(energy) = 3.53 while
fopt(performance) = 4.47 0.5
F=10

 If energy is a concern avoid F=20

oversizing beyond the 0
optimal 1 2 3 4
f
5 6 7

From Nikolic, UCB

Impact of Scaling
Gate 3 2 1.5 1 0.7 0.5 0.35 0.25 0.18 0.12
length
(m)
Vdd(V) 5 5 5 5 5 5.0/ 3.3/ 2.5/ 1.5 1.5
3.3 2.5 2.0

V T (V) 0.7 0.7 0.7 0.7 0.7 0.7/ 0.7/ 0.6/ 0.4 0.4
0.7 0.6 0.5
Tox (nm) 70 40 25 25 20 15/ 9/ 6.5/ 4.5 4
10 7 5.5
I dsatn 0.1 0.14 0.23 0.27 0.36 0.56/ 0.49/ 0.48/ 0.38 0.48
(mA/m) 0.35 0.40 0.41
I dsatp 0.06 0.11 0.14 0.19 0.27/ 0.24/ 0.23/ 0.18 0.24
(mA/m) 0.16 0.18 0.19

Inverter 800 350 250 200 160 90/ 70/ 50/ 40 32

delay 100 65 47 From MPR, 2000
(ps)
Power and Energy Design Space

Constant Variable
Throughput/Latency Throughput/Latency
Energy Design Time Non-active Modules Run Time
Logic Design
DFS, DVS
Reduced Vdd
Active Clock Gating (Dynamic
Sizing Freq, Voltage
Scaling)
Multi-Vdd
Sleep Transistors

Leakage + Multi-VT Multi-Vdd + Variable VT

Variable VT
LOW POWER DESIGN FLOW
power intent describes the
partitioning of a design into
power domains. In some cases
those are active power domains
that are being turned on and
turned off. In some cases they
are simply voltage domains,
which is different supply
voltages used in the same chip.
Describes the control signals that are used to
control the power domains.
Describes special cells that are required to
implement level shifters, retention cells …,
Various rules like :‘this domain is always on,’ or
‘this domain is off under certain conditions,’ or
‘this particular cell is used between these
domains
Ex: The Unified Power Format (UPF) is a power
specification file used in the design cycle to
implement low-power design approaches.
 POWER ESTIMATION
1)Conventional circuit simulation
2)Pattern independent probabilistic technique