Document On Shielding Of Analog Signals

Prepared By:

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AGENDA

•What is Shielding
•Why is shielding required ?
•Shielding techniques
•When Shielding should be done & when not
•General Guidelines
•Any Questions...

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 Question 1:
• What are the Characteristics of a DC
signal?
 a. Voltage
 b. Frequency
 c. Current
 d. none of the above

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 Question 2
• What are the characteristics of a clock
signal?
 a. Voltage
 b. Timing information
 c. Current
 d. All of the above
 What Is Shielding
• Signal Integrity is Most Critical Characteristic of Signal transmission in
Analog Domain
• Noise and Signal degradation are the biggest threats to signal integrity

• Noise is any unwanted electric or magnetic phenomena that corrupt the

Message signal---also termed as cross-talk

• Noise sources classified as

•  Internal: The block/device ,generating the signal

•  External: Electric/magnetic phenomena from clock /switching signals

• Protection of a Signal Integrity on a data line form the external Noise sources
can be defined as Shielding of that signal

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So Who needs to be shielded from Whom ??

•  Any signal line carrying Critical reference signals needs shielding from
any switching signal
•  For eg: Band gap reference signals, differential i/p's to comparator,etc
•  Any reference signals needs to be shielded from noisy substrate

•  Clock signals need to be shielded from any out of phase switching signals
 So How cross talk happens & how shielding is
effective ???
Parallel wirings without shield Parallel wirings with shield

Metal wires

Shield

Electric potential contour lines In this example when one wiring is

charged; the other wiring & the shield line are grounded.
 Different Scenarios to Demonstrate Noise
Coupling
(Reference signal)Victim Glitch
Signal Metal

Metal
(Clock signal) Aggressor signal

Case1: If a reference signal is routed close to a switching signal then

the reference signal will see a glitch during the switching
activity while the other may experience a delay depending upon the
strength of the driver

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Case 2
Agressor

victim

Case 2: Two switching Signals opposite in phase routed close to each

other causes delay in the signals . The delay caused depends upon the
driver strength driving the signals.

(Note : The effect varies depending upon the amplitude & also the different
switching timing instants of the signals. Presented here is one generic case .)

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Case3: glitch

Metal

Substrate plane

Switching activity in
Substrate
 So Then How to Avoid The
Coupling/Crosstalk
 Method 1: Coaxial
Shielding

Metal + 1 Lateral shield

Shield Planes
lines

Metal Signal
line
Metal - 1 Metal + 1

Capacitances between the signal line & theshield planes

(Cross sectional view) metal

Metal -1
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Method 2:Seperation
Switching Signal
2
More than min Negligible CAP
DRC

Switching/referenceSignal
1
More than min DRC Negligible CAP

Switching Signal 3

Keep Spacing between the lines More than Min

DRC

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Method 3: Ground line insertion
Clock signal
1

GND line

Clock signal
2

Inserting a Ground line between two out of phase clock

lines
 Advantages & Disadvantages
Method 1: Coaxial shielding
Coaxial shielding is used for isolation of extremely sensitivesignals whose


integrity can affect the circuit performance to a great extent

Examples: Band Gap o/p, Comparator i/p's,Clock reference signals,etc...



Advantages
 Signal is protected from any adjacent switching signal routed in the same level of
metal,metal +1 & also metal-1 level

Disadvantages
Too much coupling with the shield lines.

May slow down the switching signal. Hence only suitable for stable DC

reference signals or very slow signals.
 Method 2 : Physical Seperation

In this Method of shielding the Signal involves keeping seperation between the signals high

enough to have a negligible

coupling cap between them

• Very useful if the signals are clock signal

 Advantages

 No extra capacitance added from shielding lines as in coaxial shielding

 Disadvantages

 Spacing more than DRC results in area wastage

 Noise coupling from substrate cannot be avoided

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Method 3 : Ground line Insertion

• This method of shielding is more suitable than the physical separation for
the clock signals
• Advantages

•  Reduces the cross talk probability between the switching signals

• Disadvantages

•  This Method cannot be used for very high speed switching signal
•  This introduces additional cap on the victim & the aggressor signals
which may slow down the signals & affect the performance

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Conclusio
n
 Factors to be considered before shielding a signal
 The speed of the signal
 Why:
The added capacitance from the shielding lines may kill the high speed
signals
 The routing length of the sensitive signal
 Why??
 The signal very sensitive to noise must not be routed very long
 For very long routing even the shield lines become ineffective
 The nature of signal
 Current lines:Information contained in current. Any change in
voltage due to noise does not impact. May not need shielding
 Voltage lines: Prone to noise. Any change in voltage information
may impact the circuit performance. Hence need to be shielded

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 Which Signals do we really shield ??----Summary

Reference Signals are to be shielded from switching signals

Clock signals should not be coaxially shielded ---it may kill the signal

Two in phase signals close by need not shielding ---they actually help
each other

Two signal opposite in phase need to be shielded by a ground line

between them or spacing far apart

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 Where to connect the shield line??
The shield line must be connected to a very strong ground
Why Gnd?
 If the shield line is kept floating then it will pick spurious signal itself which
can couple to the data signal & corrupt it

Why not VDD?

 A shield line should be connected to a very low impedance path either to
clean VDD or VSS

 But VSS is considered to be more strong and a global reference for

dumping the Noise components

 All the VSS on the chip are ultimately connected to the board gnd which is
a very stable zero while all VDD's are connected to battery
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 Guidelines

Aggressor signal
R
Gnd
GND(Shield line)

Victim Signal

If this R is very large any noise coupling from the clock signal into the shield line
will see this high resistance path to the GND pad & will not be dissipated. This may
result in Ground current in the shield line itself which inturn will inject the noise into
the reference signal

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 Guidelines contd...
• A shield line must be strongly connected to ground

• Greater the number of connections tying the shield line to the power/gnd

grid smaller the coupling noise on the victim (reference signal)

Multiple grounding points

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Guidelines contd...
• To prevent any Ground current from flowing through the shield & bringing the
possible noise with it,the shield must be tied to the reference ground/Power with a
star connection
• Even if the shield line is to be connected to VDD but it must be done so only after
aDecap is connected between the VDD & VSS

Agressor signal
R
VDD Shield line
Decap
Victim Signal
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Summary

•Crosstalk between the signals can be avoided by shielding

•Only Reference Dc signals are shielded coaxially
•Out of phase Switching signals can be shielded by keeping
more than min DRC spacing or by inserting a ground line
between them
•A shield line must not be floating
•A shield line can be either connected to Gnd /Power Grid
•Greater the number of teing the Shield line to VDD or VSS
smaller is the coupling noise on the victim signal
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 References
• Junmou Zhang and Eby G. Friedman “Effect of Shield Insertion on Reducing Crosstalk
Noise between Coupled Interconnects” IEEE Circuits & systems ,paper presented in ISCAS
2004 proceedings Volume 2,pp 529-532
• Li Ding,Pinaki mazumder & David Blaauw “Crosstalk Noise Estimation Using Effective
Couplin Capacitance ” IEEE Inetrnational Symposium on Circuit and systema,Vol 5,pp. 645-
648,2002
• J.Cong D.Z.Pan and P.V Srinivas “Improved Crosstalk Modeling for Noise Contrained
Interconnect Optimization” Asia and south Pacific Design Automation Conference ,pp 373-
378,2001
• Hao Yu and Lei He “Staggered Twisted-Bundle Interconnect for Crosstalk and Delay
Reduction” IEEE Sixth international Symposium on Quality Electronic design-2005
• Dan Clein's Book “ CMOS IC LAYOUT-- Concepts,Methodologies,and Tools”

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ANY QUESTIONS ???

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