Sequential Logic Implementation

Models for representing sequential circuits

Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions)

Design procedure
State diagrams State transition table Next state functions

CS 150 - Spring 2007 Lec #6: Moore and Mealy Machines - 1

Abstraction of State Elements

Divide circuit into combinational logic and state Localize feedback loops and make it easy to break cycles Implementation of storage elements leads to various forms of sequential logic
Inputs Outputs

Combinational Logic

State Inputs Storage Elements

State Outputs

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Forms of Sequential Logic

Asynchronous sequential logic state changes occur whenever state inputs change (elements may be simple wires or delay elements) Synchronous sequential logic state changes occur in lock step across all storage elements (using a periodic waveform - the clock)

Clock
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Finite State Machine Representations

States: determined by possible values in sequential storage elements Transitions: change of state Clock: controls when state can change by controlling storage elements
001 010 111 In = 0 In = 1 100 In = 1 In = 0 110

Sequential Logic

Sequences through a series of states Based on sequence of values on input signals Clock period defines elements of sequence

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Example Finite State Machine Diagram

Combination lock from first lecture

ERR closed not equal & new reset S1 closed mux=C1 equal & new not new S2 closed mux=C2 equal & new not new not equal & new not equal & new OPEN open

S3 closed mux=C3 equal & new not new

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Can Any Sequential System be Represented with a State Diagram?

Shift Register
Input value shown on transition arcs Output values shown within state node
100 1 0 000 0 001 1 0 0 010 0 0 OUT1 IN CLK D Q D Q OUT2 D Q OUT3

1 1 101 1 1

110 1 0 0 011 111 1

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Counters are Simple Finite State Machines

Counters
Proceed thru well-defined state sequence in response to enable 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
001 010 011

Many types of counters: binary, BCD, Gray-code

000

3-bit up-counter

100

111

110

101

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Verilog Upcounter
module binary_cntr inputs clk; outputs [2:0] reg [2:0] reg [2:0] (q, clk) q; q; p;

always @(q) //Calculate next state case (q) 3b000: p = 3b001; 3b001: p = 3b010; 3b111: p = 3b000; endcase always @(posedge clk) q <= p; endmodule
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//next becomes current state

How Do We Turn a State Diagram into Logic?

Counter
Three flip-flops to hold state Logic to compute next state Clock signal controls when flip-flop memory can change

Wait long enough for combinational logic to compute new value Don't wait too long as that is low performance
OUT1 D Q CLK D Q OUT2 D Q OUT3

"1"
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FSM Design Procedure

Start with counters
Simple because output is just state Simple because no choice of next state based on input Tabular form of state diagram Like a truth-table

State diagram to state transition table

State encoding

Decide on representation of states For counters it is simple: just its value Flip-flop for each state bit Combinational logic based on encoding

Implementation

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FSM Design Procedure: State Diagram to Encoded State Transition Table

Tabular form of state diagram Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters just use value
current state 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 next state 001 1 010 2 011 3 100 4 101 5 110 6 111 7 000 0

001

010

011

000

3-bit up-counter 110 101

100

111

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Implementation
D flip-flop for each state bit Combinational logic based on encoding
C3 0 0 0 0 1 1 1 1 N3
0 0 1 1 0

C2 0 0 1 1 0 0 1 1

C1 0 1 0 1 0 1 0 1 C3
1 1

N3 0 0 0 1 1 1 1 0

N2 0 1 1 0 0 1 1 0

N1 1 0 1 0 1 0 1 0 N2
0 1 0

notation to show function represent input to D-FF

N1 := C1' N2 := C1C2' + C1'C2 := C1 xor C2 N3 := C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3

C3
1 0 0 1

N1
1 1 0 1 0

C3
1 0

C1

C1

C1

C2

C2
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C2

Implementation (cont'd)
Programmable Logic Building Block for Sequential Logic
Macro-cell: FF + logic
D-FF Two-level logic capability like PAL (e.g., 8 product terms)

DQ Q

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Another Example
Shift Register
Input determines next state
In 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 N1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 110 N2 N3 100 0 0 0 1 1 1 1 0 0 1 010 101 111 0 1 000 0 0 1 0 1 0 1 0 0 0 1 0 001 011 0 1 0 1 1 N1 := In 1 1 N2 := C1 0 0 N3 := C2 OUT1 OUT2 OUT3 0 0 0 1 0 1 D Q D Q D Q IN 1 0 CLK 1 0 1 1 CS 150 -1 Spring 2007 Lec #6: Moore and Mealy Machines - 14 1

More Complex Counter Example

Complex Counter
Repeats five states in sequence Not a binary number representation

Step 1: Derive the state transition diagram Step 2: Derive the state transition table from the state transition diagram
Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 010 101 0 1 1 1 0 1 1 0 0 011 1 0 1 1 1 0 1 1 0 0 0 0 note the don't care conditions that arise from the unused state codes 1 1 1 000 110
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Count sequence: 000, 010, 011, 101, 110

More Complex Counter Example (contd)

Step 3: K-maps for Next State Functions
C+
0 0 1 0 X

C
X 1

B+
1 1 0 0 X

C
X 1

A+
0 1 1 0 X

C
X 0

C+ := A B+ := B' + A'C' A+ := BC'

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Self-Starting Counters (contd)

Re-deriving state transition table from don't care assignment
C+
0 0 1 0 1

C
0 1

B+
1 1 0 0 0

C
1 1

A+
0 1 1 0 0

C
0 0

B Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0

111 000 100 010 011 101 110

001

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Self-Starting Counters
Start-up States Self-starting Solution
At power-up, counter may be in an unused or invalid state Designer must guarantee it (eventually) enters a valid state Design counter so that invalid states eventually transition to a valid state May limit exploitation of don't cares
111 000 100 010 011
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001

111 110 100 101

implementation on previous slide 000 110

001

010 011

101

State Machine Model

Values stored in registers represent the state of the circuit Combinational logic computes:
Next state Outputs
Function of current state and inputs Function of current state and inputs (Mealy machine) Function of current state only (Moore machine)

Inputs

output logic next state logic Current State

Outputs Next State

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State Machine Model (contd)

States: S1, S2, ..., Sk Inputs: I1, I2, ..., Im Outputs: O1, O2, ..., On Transition function: Fs(Si, Ij)
Inputs output logic next state logic Current State Outputs Next State

Output function: Fo(Si) or Fo(Si, Ij)

Next State State Clock 0 1 2 3 4 5

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First Midterm Exam15 February 2007

Topics to be covered: Combinational logic design From spec to truth table to K-map to Boolean Expression Canonical forms of Boolean Expressions Conversions of AND-OR logic to NAND or NOR logic Two level logic implementations using gates, PLA, MUX, DEC, ROM, Xilinx CLB FPGA structures Comparing implementation complexities/figures of merit Combinational Verilog (lab expertise!) Basic Sequential logic design Flip flop behavior, analysis, and timing diagrams Using flip flops to design registers, shifters, counters From spec to state diagram to Sequential Verilog Amount of FSM implementation through end of today

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First Midterm Exam15 February 2007

Exam mechanics Worth ONLY 10% of course grade In class, designed for 1 hour, full 80 minutes available WILL TAKE PLACE IN 125 CORY LABORATORY!!! No Blue Bookall work to be done on the exam paper! Bring pencil and eraserDUMB to use pen! Cheating = 0 on examDO NOT DO IT! F in class plus letter to file for second offense Closed Book, Closed Notes BUT 8.5 x 11 two-sided crib sheet OK Developing your crib sheet is a great way to study Dont forget old exams and solutions are all on-line No calculators, PDAs, laptops, camera phones, icq to experts Write assumptions if problem spec is ambiguous Difficult to ask questions during the exam itself Written regrade appeals policy
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Example: Ant Brain (Ward, MIT)

Sensors: Actuators: Goal: Strategy: L and R antennae, 1 if in touching wall F - forward step, TL/TR - turn left/right slightly find way out of maze keep the wall on the right

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Ant Brain

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Ant Behavior
A: Following wall, touching Go forward, turning left slightly B: Following wall, not touching Go forward, turning right slightly

C: Break in wall Go forward, turning right slightly E: Wall in front Turn left until...

D: Hit wall again Back to state A

F: ...we are here, same as state B

LOST: Forward until we touch something

G: Turn left until...

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Designing an Ant Brain

State Diagram
L+R LOST (F) L R L+R E/G (TL) L R R L R B (TR, F) L A (TL, F) L R

C (TR, F)

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Synthesizing the Ant Brain Circuit

Encode States Using a Set of State Variables
Arbitrary choice - may affect cost, speed

Use Transition Truth Table

Define next state function for each state variable Define output function for each output

Implement next state and output functions using combinational logic

2-level logic (ROM/PLA/PAL) Multi-level logic Next state and output functions can be optimized together

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Transition Truth Table

Using symbolic states and outputs
LOST (F) L R state L R LOST 0 0 LOST 1 LOST 1 A A A B B 0 0 0 1 1 0 1 next state LOST E/G E/G B A E/G C A outputs F F F TL, F TL, F TL, F TR, F
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L+R L+R E/G (TL) L R B (TR, F) R L R L A (TL, F) R C (TR, F)

L R

TR, F

Synthesis
5 states : at least 3 state variables required (X, Y, Z)
State assignment (in this case, arbitrarily chosen)
LOST - 000 E/G A state L R X,Y,Z 000 0 0 000 0 1 ... ... ... 010 0 0 010 0 1 010 1 0 010 1 1 011 0 0 011 0 1 next state X', Y', Z' 000 001 ... 011 010 001 001 100 010 outputs F TR TL 1 0 1 0 ... 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 it now remains to synthesize these 6 functions B C - 001 - 010 - 011 - 100

CS 150 - Spring 2007 Lec #6: Moore and Mealy Machines - 29

Synthesis of Next State and Output Functions

state inputs X,Y,Z L R 000 0 0 000 - 1 000 1 001 0 0 001 - 1 001 1 010 0 0 010 0 1 010 1 011 - 0 011 - 1 100 - 0 100 - 1 next state outputs X+,Y+,Z+ 000 001 001 011 010 010 011 010 001 100 010 100 010 F TR TL 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 e.g. TR = X + Y Z X+ = X R + Y Z R = R TR

CS 150 - Spring 2007 Lec #6: Moore and Mealy Machines - 30

Circuit Implementation
Outputs are a function of the current state only - Moore machine

output logic L R next state logic Next State X+ Y+ Z+

F TR TL

Current State

CS 150 - Spring 2007 Lec #6: Moore and Mealy Machines - 31

Verilog Sketch
module ant_brain (F, TR, TL, L, R) inputs L, R; outputs F, TR, TL; reg X, Y, Z; assign F = function(X, Y, Z, L, R); assign TR = function(X, Y, Z, L, R); assign TL = function(X, Y, Z, L, R); always @(posedge clk) begin X <= function (X, Y, Z, L, R); Y <= function (X, Y, Z, L, R); Z <= function (X, Y, Z, L, R); end endmodule

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Dont Cares in FSM Synthesis

What happens to the "unused" states (101, 110, 111)? Exploited as don't cares to minimize the logic

If states can't happen, then don't care what the functions do if states do happen, we may be in trouble
L R 000 (F) 101 L+R 001 (TL) L R 011 (TR, F) 111 R L R 110 L+R L 010 (TL, F) R 100 (TR, F) L R

Ant is in deep trouble if it gets in this state

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State Minimization
Fewer states may mean fewer state variables High-level synthesis may generate many redundant states Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same Two conditions for two states to be equivalent:
1) Output must be the same in both states 2) Must transition to equivalent states for all input combinations

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Ant Brain Revisited

Any equivalent states?
L+R LOST (F) L R L+R E/G (TL) L R R L R B (TR, F) L A (TL, F) L R

C (TR, F)

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New Improved Brain

Merge equivalent B and C states Behavior is exactly the same as the 5-state brain We now need only 2 state variables rather than 3
L+R LOST (F) L R L+R E/G (TL) L R R L R R B/C (TR, F) L A (TL, F) L R

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New Brain Implementation

state inputs X,Y 00 00 00 01 01 01 10 10 10 11 11 L R 0 0 - 1 1 0 0 - 1 1 0 0 0 1 1 - 0 - 1 next state outputs X',Y' 00 01 01 11 01 01 11 10 01 11 10 F TR TL 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0
L F X 1 1 1 1 0 0 0 0 Y 1 1 1 1 1 1 1 1 R L L

X+

X 0 0 0 0 1 0 0 0 Y 1 1 1 1 1 1 0 0 R

Y+

X 0 1 1 1 1 0 0 0 Y 1 0 0 1 1 0 1 1 R

TR

X 0 0 0 0 0 0 0 0 Y 1 1 1 1 0 0 0 0 R

TL

X 0 0 0 0 1 1 1 1 Y 0 0 0 0 1 1 1 1 R

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Sequential Logic Implementation Summary

Models for representing sequential circuits
Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic

Finite state machine design procedure

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