Asynchronous (Ripple) Counter

Synchronous Counter
• At the end of this chapter, students should
be able to:-
• Differentiate between asynchronous counter and
synchronous counter. .
• Design an asynchronous counter.
• Design a synchronous counter.
• Analyse a synchronous counter.

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 • Flip-flops are wired together to form binary counters.
• They are used to measure the frequency of a signal and are used in
digital clock.
• Counters characteristics:
– Modulus of counter - the maximum number of counts to complete the
counting cycles.
– Can count either up or down.
– Can operate asynchronously (ripple) or synchronously.
– Free running or self stopping.

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 • Also known as ripple counter.
• Example: Modulo-4 or mod-4 counter.
• A counter that counts from 00 to 11 (0 to 3) is called modulo-4 or
mod-4 counter.
• The modulus of a counter is the number of counts the counter goes
through.
• Note that each flip-flop is in its toggle mode.
• Each flip-flop output drives the CLK input of
the next flip-flop.
1 J SET
Q 1 J SET Q A B

Clock pulse A B
1 K Q 1 K CLR Q
CLR

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 • The clock pulse is applied to the clock of flip-flop A.
• The output of flip-flop A is connected to the clock of flip-flop B.
• Flip-flop A will toggle (change to its opposite state) each time a clock
pulse make a transition.
• The output of flip-flop A will act as the clock for flip-flop B, and so
the output B will toggle each time A goes from transition.
• The counting sequence is 00, 01, 10, 11.

CLK 0 1 2 3 4 5 6 7 8 9

AB 00 01 10 11 00 01 10 11 00 01

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 • Synchronous counters can be designed to produce special purpose count
sequences of nonconsecutive numbers (0, 2, 4,6).
• Excitation table

Present Next J K Mode

State (PS) State
(NS)
0 0 0 x Hold (00) or Reset (01)
0 1 1 x Toggle(11) or Set (10)
1 0 x 1 Toggle (11) or Reset (01)
1 1 x 0 Hold (00) or Set (10)
0X X0
1X

0 1

X1

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Example:

Design a synchronous counter t0 count the following

sequence: 0, 1, 2,3,0….
Steps: 1 Draw the state transition diagram 0 1 2 3

2 Derive the excitation table

Present State Next State JK

0X X0
PS A B NS A’ B’ JA KA JB KB 1X

0 0 0 1 0 1 O x 1 x 0 1

1 0 1 2 1 0 1 x x 1 X1

2 1 0 3 1 1 x 0 1 x
3 1 1 0 0 0 x 1 x 1

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 3 Simplify the JK expressions using Karnaugh map

A A A A

B 0 x B x 0

B 1 x B x 1

JA = B KA= B

A A A A

B 1 1 B x x

B x x B 1 1
JB = 1 KB = 1

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 4 Draw the synchronous counter circuit

A B

1
J SET Q J SET Q

CLR CLR
K Q K Q

JA = B JB = 1
KA = B KB = 1

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Example:

Design a synchronous counter using JK flip-flops t0 produce the following

sequence:

0 2 3

4
7 5

0X X0
1X

0 1

X1
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 0X X0
1X

0 1
Steps:
X1
Present State Next State JK
PS A B C NS A’ B’ C’ JA KA JB KB JC KC
0 0 0 0 2 0 1 0 0 x 1 x 0 x
1 0 0 1 x x x x x x x x x x
2 0 1 0 0 0 0 0 0 x x 1 0 x
3 0 1 1 4 1 0 0 1 x x 1 x 1
4 1 0 0 5 1 0 1 x 0 0 x 1 x
5 1 0 1 3 0 1 1 x 1 1 x x 0
6 1 1 0 x x x x x x x x x x
7 1 1 1 3 0 1 1 x 1 x 0 x 0

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 A B AB AB AB A B AB AB AB A B AB AB AB
C 0 0 x x C x x x 0 C 1 x x 0

C x 1 x x C x x 1 1 C x x x 1

JA = C KA = C JB = A + C

A B AB AB AB A B AB AB AB A B AB AB AB

C 0 0 x 1 C x x x x C x x x x

C x x x x C x 1 0 0 C x 1 0 0

JC = A KB = A KC = A

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 4 Draw the synchronous counter circuit

JA = C JB = A + C JB = A
KA = C KB = A KB = A

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 Analyse the following synchronous counter circuit.
A B C

1
J SET
Q J SET
Q J SET
Q

K CLR Q K CLR Q K CLR Q

1 Identify the J and K expressions

JA = BC JB = C JC = 1
KA =BC KB = C KC = 1

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 Input Output

2 Derive the excitation table. CLOCK J K Q Mode

0 0 Q Hold
JA = BC JB = C JC = 1 0 1 0 Reset

KA =BC KB = C KC = 1 1 0 1 Set
1 1 Q Toggle

Present State Next State JK

PS A B C NS A’ B’ C’ JA KA JB KB JC KC
0 0 0 0 1 0 0 1 0 0 0 0 1 1
1 0 0 1 2 0 1 0 0 0 1 1 1 1
2 0 1 0 3 0 1 1 0 0 0 0 1 1
3 0 1 1 4 1 0 0 1 1 1 1 1 1
4 1 0 0 5 1 0 1 0 0 0 0 1 1
5 1 0 1 6 1 1 0 0 0 1 1 1 1
6 1 1 0 7 1 1 1 0 0 0 0 1 1

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 3 Draw the state transition diagram

0 1 2 3 4 5 6 7

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