It is better to light one small candle than to curse the darkness.

Confucius

FSM – Finite State Machines

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Finite State Machines

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Summary
A FSM is used to model a system that transits among a finite
number of internal states.
The transitions depend on the current state and external
input.
◦ Unlike a regular sequential circuit, the state transitions of an FSM
do not exhibit a simple, repetitive pattern.
◦ Its next-state logic is usually constructed from scratch and is
sometimes known as “random” logic.

This is different from the next-state logic of a regular

sequential circuit, which is composed mostly of “structured”
components, such as incrementors and shifters.

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Summary
In practice, the main application of an FSM is
◦ to act as the controller of a large digital system,
◦ which examines the external commands and status and activates proper
control signals to control operation of a data path, which is usually
composed of regular sequential components.

This is known as an FSMD (finite state machine with data path).

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 FSM – general architecture (Mealy
machine)

(State
excitation Memory) pr_state outputs
inputs Next-state Output Logic
Next-state
Logic (F) (G)
Logic (F)

Clk
clocked synchronous state machine - general structure

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 Moore Machine

(State
excitation Memory) pr_state outputs
inputs Next-state Output Logic
Next-state
Logic (F) (G)
Logic (F)

Clk

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 Mealy and Moore outputs

(State
excitation Memory) pr_state Mealy
inputs Next-state Output Logic
Next-state
Logic (F) (G1) outputs
Logic (F)

Clk

Output Logic Moore

(G2) outputs

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 Pipelined Outputs

inputs (State
Output
excitation Memory) pr_state Pipelined
Next-state Output Logic Pipeline
Next-state
Logic (F) (G) Memory outputs
Logic (F)

Clk

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FSM representation
An FSM is usually specified by
◦ an abstract state diagram or
◦ ASM chart (algorithmic state machine chart)

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State diagram – single node
Mo – Moore Output
Me – Mealy Output

state_name
Mo<=value

logic_expresion / Me <= value logic_expresion/ Me <= value

to other state to other state

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ASM chart

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Finite State Machines
Finite state machines (FSM) constitute a special modeling
technique for sequential logic circuits.
Such a model can be very helpful in the design of certain
types of systems, particularly those whose tasks form a
well-defined sequence (digital controllers, for example).

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Single-phase state machine
Upper section (gates)

Input Output
Combinational
logic

pr_state next_state

Clk Sequential
logic
Reset

Lower section (flip-flops)

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 Upper section (gates)

Sequential Logic Input Combination

al
Output

logic
pr_state next_state

Clk Sequential
process (reset, clock) Reset logic
begin
Lower section (flip-flops)
if (reset = '1') then
pr_state <= initial_state;
elsif (clock'event and clock = '1') then
pr_state <= next_state;
end if;
end process;

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 Upper section (gates)

Input Combination Output

Combinational Logic al
logic
process (input, pr_state) pr_state next_state

begin
Clk Sequential
case pr_state is
Reset logic
when state0 =>

if (input = ...) then Lower section (flip-flops)

output <= <value>;

next_state <= state1; when state2 =>

else ... if (input = ...) then
end if; output <= <value>;
next_state <=
when state1 => state2;
if (input = ...) then else ...
output <= <value>; end if;
next_state <= state2; ...
else ... end case;
end if; end process;

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Design Styles

a. Style #1 b. Style #2

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 Design Style #1
library ieee;
use ieee.std_logic_1164.all;

entity <entity_name> is

port ( input: in <data_type>;

reset, clock: in std_logic;

output: out <data_type>);

end <entity_name>;

architecture <arch_name> of <entity_name> is

type state is (state0, state1, state2, state3, ...);

signal pr_state, next_state: state;

begin

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Design Style #1
---------- lower section: ------------------------
process (reset, clock)
begin
if (reset = '1') then
pr_state <= state0;
elsif (clock'event and clock = '1') then
pr_state <= next_state;
end if;
end process;

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Design Style #1
---------- upper section: ------------------------
process (input, pr_state)
begin
case pr_state is
when state0 =>
if (input = ...) then
output <= <value>;
next_state <= state1;
else ...
end if;

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 Design Style #1
when state1 =>

if (input = ...) then

output <= <value>;

next_state <= state2;

else ...

end if;

when state2 =>

if (input = ...) then

output <= <value>;

next_state <= state3;

else ...

end if;

...

end case;

end process;

end <arch_name>;

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a. Style #1 b. Style #2

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 Design Style #2 (Stored/pipelined
Output)
library ieee;

use ieee.std_logic_1164.all;

entity <ent_name> is

port ( input: in <data_type>;

reset, clock: in std_logic;

output: out <data_type>);

end <ent_name>;

architecture <arch_name> of <ent_name> is

type states is (state0, state1, state2, state3, ...);

signal pr_state, next_state: states;

signal temp: <data_type>;

begin

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Design Style #2 (Stored Output)
---------- lower section: --------------------------
process (reset, clock)
begin
if (reset='1') then
pr_state <= state0;
elsif (clock'event and clock = '1') then
output <= temp;
pr_state <= next_state;
end if;
end process;

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 Design Style #2 (Stored Output)
---------- upper section: --------------------------

process (pr_state)

begin

case pr_state is

when state0 =>

temp <= <value>;

if (condition) then next_state <= state1;

...

end if;

when state1 =>

temp <= <value>;

if (condition) then next_state <= state2;

...

end if;

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Design Style #2 (Stored Output)
when state2 =>
temp <= <value>;
if (condition) then next_state <= state3;
...
end if;
...
end case;
end process;
end <arch_name>;

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