CAD FOR VLSI

III Year – I Semester

22.07.2023
 Course Objectives
• To make the students familiarize with the VLSI design process,
partitioning, floor planning, placement, routing and physical
design automation of FPGAs.
 Course outcomes
• Upon successful completion of the course, the students will
be able to
• CO1: understand various methodologies for the design of VLSI
systems.
• CO2: design the VLSI circuits using physical design steps.
• CO3: implement the circuits in FPGA using physical design
steps.
 Course Content
• UNIT I: Introduction to VLSI Design: The VLSI design process,
layout styles, Difficulties in physical design, Definitions and
Notation.

• UNIT II: Circuit Partitioning: Introduction, Problem definition,

Cost function and constraints, Approaches to Partitioning
Problem.
 Course Content
• UNIT III: Floorplanning and Placement: Problem definition,
Approaches to Floorplanning, Circuit representation, Wire
length estimation, Types of placement problem, Placement
algorithms.

• UNIT IV: Routing: Types of local routing problems, Area

Routing, Channel Routing, Global Routing
 Course Content
• UNIT V: Physical design automation of FPGAs: Physical design
cycle for FPGAs, Partitioning, Routing.
 History of CAD VLSI
• The First Research Paper on CAD appeared in 1955.
• CAD started being recognized as indispensable as early as
1960.
• Now for nearly two decades, CAD of digital systems has
become a mature area.
• There are three general aspects of CAD:
• (i) Synthesis
• (ii) Verification
• (iii) Design management
• This subject deals with synthesis aspect.
 Synthesis
• Synthesis is known as the problem of obtaining a lower level
representation of a digital system from a higher level
representation of the same system
• When the higher level representation is a behavioral
description and the lower level is a structural description, the
synthesis process from the higher level to the lower level is
known as high-level synthesis
• When both the higher and lower levels are structural
representations, the process is called physical synthesis
• We are mostly concerned physical synthesis, i.e., partitioning,
floor planning, placement, and routing
Gaski’s Chart
 Organization of the subject
• This subject has 5 Chapters. The chapters are organized in a
sequence similar to the physical synthesis process flow.
• Chapter 1, motivates the student towards a study of physical
design automation of integrated circuits. Layout, which is one
of the physical representation of the digital circuits, is
discussed in detail, along with its styles. This chapter also
introduces basic terminologies used in CAD for VLSI.
• Chapter 2 deals with the problem of circuit partitioning, and
various algorithms used to solve the partitioning problems
 Organization of the subject
• Chapter 3 discusses floor planning and placement process steps
in physical synthesis. It also discusses different algorithms used
to solve floor planning and placement problems
• Chapter 4 illustrates different types of routing and algorithms
used for solving routing problems
• Chapter 5 describes physical design automation aspects of
FPGA synthesis. In this approach only placement and routing
aspects of physical synthesis aspects are discussed because the
FPGA contains array of functional blocks repeated across the
chip, which does not require floor planning and placement
aspects.
 Text Books
• TEXT BOOKS:
• S.H.Gerez, “Algorithms for VLSI Design Automation”, John
Wiley & Sons,2002.
• Sadiq M. Sait, Habib Youssef, “VLSI Physical Design
Automation: Theory and Practice”, World Scientific 1999.
• REFERENCE BOOKS:
• N.A. Sherwani, “Algorithms for VLSI Physical Design
Automation”, Kluwer Academic Publishers, 2002.
• Steven M.Rubin, “Computer Aids for VLSI Design”, Addison
Wesley Publishing 1987.