S.B.

Nimbekar
Dept. of Computer Engineering
Sinhgad Institute of Technology, Lonavala

Email:- sbn.sit@sinhgad.edu
Contact No.+91-8087799608

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Unit III: Memory Management

• Global Descriptor Table,

• Local Descriptor Table,
• Interrupt Descriptor Table,
• GDTR, LDTR, IDTR.
• Formats of Descriptors and Selector,
• Segment Translation,
• Page Translation,
• Combining Segment and Page Translation.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Descriptor Tables

• There are three types of tables on the Intel386 DX which hold

descriptors:
– Global Descriptor Table,
– Local Descriptor Table, and
– Interrupt Descriptor Table.
• All of the tables are variable length memory arrays.
• They can range in size between 8 bytes and 64K bytes.
• Each table can hold up to 8192 8 byte descriptors.
• The upper 13 bits of a selector are used as an index into the
descriptor table.
• The tables have registers associated with them (the GDTR, LDTR,
and the IDTR), which hold the 32-bit linear base address, and the
16-bit limit of each table.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Global Descriptor Table

• The Global Descriptor Table (GDT) contains descriptors

which are possibly available to all of the tasks in a system.
• The GDT can contain any type of segment descriptor except
for descriptors which are used for servicing interrupts (i.e.
interrupt and trap descriptors).
• Every Intel386 DX system contains a GDT.
• Generally the GDT contains code and data segments used
by the operating systems and task state segments, and
descriptors for the LDTs in a system.
• The first slot of the Global Descriptor Table corresponds to
the null selector and is not used. The null selector defines a
null pointer value.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Local Descriptor Table

• LDTs contain descriptors which are associated with a given task.

• Generally, operating systems are designed so that each task has a
separate LDT.
• The LDT may contain only code, data, stack, task gate, and call gate
descriptors.
• LDTs provide a mechanism for isolating a given task's code and data
segments from the rest of the operating system, while the GDT
contains descriptors for segments which are common to all tasks.
• A segment cannot be accessed by a task if its segment descriptor
does not exist in either the current LDT or the GDT.
• This provides both isolation and protection for a task's segments,
while still allowing global data to be shared among tasks.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Interrupt Descriptor Table

• The IDT contains the descriptors which point to the

location of up to 256 interrupt service routines.
• The IDT may contain only task gates, interrupt gates,
and trap gates.
• The IDT should be at least 256 bytes in size in order to
hold the descriptors for the 32 Intel Reserved
Interrupts.
• Every interrupt used by a system must have an entry in
the IDT.
• The IDT entries are referenced via INT instructions,
external interrupt vectors, and exceptions.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

GDT, LDT & IDT

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

GDTR, LDTR & IDTR

• GDTR: 48 bit
• LDTR: 16 bit
• IDTR: 48 bit

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Descriptors

• It provides the processor with data it needs to

map a logical address into a linear address
• Created by compilers, linkers, loaders, or the
OS, not by applications programmers
• Two general purpose descriptor formats
– Used for applications code and data segments
– Used for special system segments

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Descriptor Formats

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Segment Descriptor fields
• Base: 32-bit value, defines location of the segment
within the 4GB linear address space
• Limit: 20-bit value, Defines the size of the segment,
depending on Granularity bit (G)
• Granularity Bit (G): Specifies unit of LIMIT field
– 0: byte granular, to define a limit of up to 1MB
– 1: Page granular, to define a limit of up to 4GB
• TYPE: Distinguish between various kinds of
descriptors
• DPL: Descriptor privilege level
• AVL: Available for system programmer
• P: Present
• A: Accessed
Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala
Selectors

• RPL: Requestor’s Privilege Level

• TI: Tab Indicator (0: GDT, 1: LDT)
• Index: Selects one of 8192 descriptor, processor
multiplies this index value by 8 and adds the
result in base address of the descriptor table
(From GDTR or LDTR)
• Null Selector: A selector with Index & TI = Zero
Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala
Segment Registers

• 80386 stores information from descriptors in

segment registers, thereby avoiding the need to
consult a descriptor table every time it accesses
memory
• Visible portion (manipulated by programs) and an
invisible portion (manipulated by processor)

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala
Memory Management

• 80386 translates logical address to physical address in two steps

– Segment Translation
• Logical to linear
– Page Translation
• Linear to Physical

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Segment Translation

• To perform this translation, the processor uses

the following data structures
– Selectors
– Segment Registers
– Descriptor tables
– Descriptors

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Page Translation

• In the second phase of address transformation, the

80386 transforms a linear address into a physical
address.
• This phase of address transformation implements
the basic features needed for page-oriented virtual-
memory systems and page-level protection.
• The page-translation step is optional.
• Page translation is in effect only when the PG bit of
CRO is set.
• This bit is typically set by the operating system
during software initialization.
Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala
Page Frame

• A page frame is a 4K-byte unit of contiguous

addresses of physical memory.
• Pages begin on 4K - byte boundaries and are
fixed in size.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Page Translation

• The addressing mechanism uses DIR field as an index into a page

directory.
• PAGE field as an index into the page table determined by the page
directory.
• OFFSET field to address a byte within the page determined by the
page table.

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Page Table

• A page table is simply an array of 32-bit page specifier.

• Two levels of tables are used to address a page of
memory.
• At the higher level is a page directory.
• The page directory addresses up to 1 K page tables of the
second level.
• A page table of the second level addresses up to 1 K
pages.
• All the tables addressed by one page directory, therefore,
can address 1 M pages (220).
• Because each page contains 4 Kbytes 212 bytes), the
tables of one page directory can span the entire physical
address space of the 80386 (220 times 212 = 232).

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

PDE & PTE

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala

Combining Segment and Page Translation

Prof S B Nimbekar, Dept of Computer Engineering, SIT, Lonavala