CACHE MEMORY

 LUQMAN ASIF
 18-NTU-1126
WHAT IS CACHE MEMORY?

• PORTION OF HIGH SPEED MEMORY.

• HERE MACHINE KEEPS THE COPY OF DATA.
• CLOSER TO A PROCESSOR CORE.
• REDUCES AVERAGE COST.
• TIME AND ENERGY
• FASTER THE DATA TRANSFER.
 TRANSFERRING OF
DATA BY CACHE
MEMORY

•HERE COMPUTER
SHORTEN THE DATA
TRANSFERRING PATH
•CREATE PATH FROM
CACHE MEMORY TO
REGISTER.
 CACHE LEVELS.

• MOST CPUS HAVE INDEPENDENT CACHE.

• INSTRUCTION AND DATA CACHES
• HERE DATA CACHE USUALLY ORGANIZED MORE CACHE LEVELS
i. L1
ii. L2
iii. L3
 LEVEL-1 CACHE

• ALMOST ALL THE COMPUTERS HAVING CACHE ARE USING

SPLIT L1 CACHE.
• L1D FOR DATA
• L1I FOR INSTRUCTION
• BUILT ONTO THE MICROPROCESSOR CHIP
• FOR EXAMPLE
• INTEL MMX MICROPROCESSOR COMES WITH 32 THOUSANDS
BYTES OF L1
 LEVEL-2 CACHE

• DOES NOT SPLIT.

• FOUND ON THE EXPANSION CARD.
• AS L2 CACHE MEMORY IS ON SEPARATE CHIP.
• ACT AS COMMONLY RESPIRATORY.
• DEDICATED TO MULTICORE PROCESSOR.
• DOES NOT SHARE BETWEEN THE CORES.
• ITS POPULAR SIZE IS 1,024 KB
 LEVEL -3 CACHE

• BUILT ON THE MOTHERBOARD

• DOES NOT SPLIT.
• SHARED BETWEEN THE CORES.
• TYPICALLY SLOWER THAN OTHERS.
• BIGGER IN SIZE.
 CACHE MISS
WHAT IS CACHE MISS?

• FAILED ATTEMPT TO READ DATA

• RESULTS IN MEMORY ACCESS
• THUS CAUSE LONGER LATENCY
• DELAY THE TRANSFERRING
 KINDS OF CACHE MISS

• INSTRUCTION READ MISS

• DATA READ MISS
• FROM INSTRUCTION CACHE
CAUSE LARGEST DELAY
• FROM DATA CACHE
CAUSE SMALLER DELAY

• DATA WRITE MISS

• CAUSE SHORTEST DELAY
ASSOCIATIVITY
o DIRECT MAPPED o TWO WAY SET
CACHE ASSOCIATIVITY
• EACH LOCATION CAN GO IN ONE ENTRY • EACH LOCATION CAN GO IN TWO
• DOES NOT HAVE REPLACEMENT POLICY ENTRY
• IT HAS REPLACEMENT
• NEEDS TO BE MUCH LARGER
• SMALLER THAN DIRECT MAPPED
Thank you