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Ch11 Interrupt
Ch11 Interrupt
INTERRUPTS
Topics Covered
Transferring Data Between the CPU and I/O Device Types of Interrupts Processing Interrupts Interrupts Hardware and Priority Implementing Interrupts Inside the CPU
What is Interrupts ?
Interrupts is a mechanism for alleviating the delay caused by this uncertainty and for maximizing system performance.
Types of Interrupts
External Interrupts
Internal Interrupts
Software Interrupts
Processing Interrupts
Who services the interrupt? An interrupt triggers a sequence of events to occur within the computer system. These events acknowledge the interrupt and perform the actions necessary to service the interrupt. These events only occur if the interrupt is enabled. Interrupt is also serviced by software which is written by the user, is called the handler, essentially a subroutine.
Sequence of Events
Do nothing(until the current instruction has been executed) Get the address of the handler routine.(vector interrupts only) Invoke the handler routine
Hardware and Timing of a non-vectored interrupt for a single device. Hardware and Timing of a vectored interrupt for a single device. Hardware of multiple non-vectored interrupts
(a)Hardware of a non-vectored interrupt for a single device An external device sent an interrupt to the CPU by asserting its interrupt request (IRS) signal. When the CPU is ready to process the interrupt request, it assert the its interrupt acknowledge signal (IACK), thus informing the I/O device that is ready to proceed. (b)Timing of a non-vectored interrupt for a single device The device set the IRQ low, which cause the CPU set the IACK low. As the handler routine proceeds, it transfers data between the CPU and the interrupting device.
Interrupt Request Interrupt Acknowledge Device Data bus Data (a) IRQ IACK Data (b)
valid
(a)Hardware of a vectored interrupt for a single device A vector interrupt is more complex. After acknowledge the interrupt, the CPU must input an interrupt vector from the device and call an interrupt service routine(handler); the address of this routine is a function of the vector. (b)Timing of a vectored interrupt for a single device
Device #0
Device #1
CPU
IRQ n IACK n Device #n
Data
Parallel Priority
Daisy Chaining:
The interrupt request signals from the devices are wire-ORed together. When the CPU receives an active IRQ input, it cannot know which device generated the interrupt request. It sends out an acknowledge signal and leaves it to the devices to work that out
among themselves.
Interrupt Acknowledge IACK Interrupt Request
IACKin IRQ Device #n D IACKout
CPU
IRQ
Vector
Data
Possible values of IACKin and IACKout and their states The invalid state (IACKin = 0 and IACKout = 1) is shown to account for all possible value of IACKin and IACKout, but a device should never be in this state.
IACKin 1 IACKout 1 State
Device has priority to interrupt but does not
1
0 0
0
1 0
IRQ
Interrupt request
Vector
CPU
Data
IRQ Device #0
IACK
IRQ Device #1
IRQ Device #n
The most difficult part of handling the interrupt is recognizing it and accessing the states to process the interrupt. This is done every execute cycle, and could be done in one or two ways.
1. Using separate FETCH1 and INT1 states The branches that go to state FETCH1 are broken into two branches. If interrupts are enabled (IE=1) and an interrupt is pending (IP=1), these states branch to the beginning of the interrupt handler routine, state INT1, rather than to FETCH1. If either the IE or IP is 0, no interrupt is processed and the CPU proceeds to FETCH1 to continue processing instructions.
IEVIP
execute routines
FETCH1
execute routines
FETCH1
INT1
IE^IP
2.Modifying FETCH1 to support interrupts The micro-operations associated with the state can be modified. State FETCH1 would consist of two sets of micro-operations. The CPU could branch to either FETCH2 or INT2.
IEVIP FETCH 2 FETCH 1 FETCH 2 Modified FETCH
IE^IP
INT 2
1. CPU pushes the return address on to the stack 2. Reads in the interrupt vector 3.Jumps to the address corresponding to this vector, 1111(vector) 0000.