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Introduction to Computing
Chapter 0

Sepehr Naimi

www.NicerLand.com
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 Topics
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• Internal organization of computers

– The different parts of a computer
• I/O
• Memory
• CPU
– Connecting the different parts
• Connecting memory to CPU
• Connecting I/Os to CPU
– How computers work

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 Internal organization of computers
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• CPU
• Memory
• I/O
– Input
• E.g. Keyboard, Mouse, Sensor
– Output
• E.g. LCD, printer, hands of a robot

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 Memory
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• Everything that can store, retain, and recall

information.
– E.g. hard disk, a piece of paper, etc.

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 Memory characteristics
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• Capacity
– The number of bits that a memory can store.
• E.g. 128 Kbits, 256 Mbits
• Organization
– How the locations are organized 4 bits
0

128 locations
• E.g. a 128 x 4 memory has 128 locations,
1
2

4 bits each

…
• Access time 127

– How long it takes to get data from memory

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 Memory
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• Semiconductors

• Non-semiconductors The pictures are copied from http://www.wikipedia.org/

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 Semiconductor memories
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• ROM RAM •
– Mask ROM SRAM (Static RAM) –
– PROM (Programmable DRAM (Dynamic RAM) –
ROM) NV-RAM (Nonvolatile –
– EPROM (Erasable RAM)
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM

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 Memory\ROM\ Mask ROM
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• Programmed by the IC manufacturer

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 Memory\ROM\ PROM (Programmable ROM)
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• OTP (One-Time Programmable)

– You can program it only once

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 Memory\ROM\ EPROM (Erasable Programmable ROM)
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• UV-EPROM
– You can shine ultraviolet (UV) radiation
to erase it
– Erasing takes up to 20 minutes
– The entire contents of ROM are erased

2764

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 Memory\ROM\ EEPROM (Electrically Erasable
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Programmable ROM) BIHE university

• Erased Electrically
– Erased instantly
– Each byte can be erased separately

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 Memory\ROM\ Flash ROM
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• Erased in a Flash
• the entire device is erased at once

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 Semiconductor memories
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• ROM RAM •
– Mask ROM SRAM (Static RAM) –
– PROM (Programmable DRAM (Dynamic RAM) –
ROM) NV-RAM (Nonvolatile –
– EPROM (Erasable RAM)
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM

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 Memory\RAM\ SRAM (Static RAM)
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• Made of flip-flops (Transistors)

• Advantages: 2K x 8
– Faster SRAM

– No need for refreshing

• Disadvantages:
– High power consumption
– Expensive

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 Memory\RAM\ DRAM (Dynamic RAM)
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• Made of capacitors
• Advantages:
– Less power consumption
– Cheaper
– High capacity
• Disadvantages:
– Slower
– Refresh needed

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 Memory\RAM\ NV-RAM (Nonvolatile RAM)
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• Made of SRAM, Battery, control circuitry

• Advantages:
– Very fast
– Infinite program/erase cycle
– Non-volatile
• Disadvantage:
– Expensive

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 Internal parts of computers\CPU
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• Tasks:
– It should execute instructions
• It should recall the instructions one after another
and execute them

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 Connecting memory to CPU
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• Memory pin out

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 Connecting memory
Writing
Reading memory to CPU
to memory
from

Address
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Address
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CS
CS
OE
Data
Data
WE
WE
Time
Time

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 Connecting I/Os to CPU
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• CPU should have

lots of pins! Mouse

Network
CPU Keyboard

Sound Card
Graphic Card

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 Connecting I/Os to CPU using bus
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Address bus

Data bus
Write
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

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 Connecting I/Os and Memory to CPU
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Address bus

Data bus
Write
Control bus Read

CPU I/O 0 I/O 1 I/O 2 I/O n

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 Connecting I/Os and memory to CPU using bus
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0
1

How could we manage it? 2

3

0
Address bus

Data bus
Write
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

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 Connecting I/Os and Memory to CPU using bus
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(Peripheral I/O) BIHE university

0
1
..
63

Address bus

Data bus
Write
Control bus Read
IO/MEM
CPU
I/O 0 I/O 1 I/O 2 I/O n

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 Connecting I/Os and Memory to CPU using bus
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(Memory Mapped I/O) BIHE university

0 The logic circuit

1 enables CS
..
How could we make the logic 15
when address is
circuit? between 0 and
15
Logic circuit
Address bus

Data bus
Solution
Control 1.
bus Write
Write the address range in binary
Read
2. Separate the fixed part of address

CPU3. Using a NAND, design a logic circuit whose output

activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0  0 0 0 0 0 0 0 0 a4
I/O 16 I/O 17 I/O a5
18
a6
I/OCS
n
To address15  0 0 0 0 1 1 1 1 a7

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 Another example for address decoder
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• Design an address decoder for address of 300H

to 3FFH.

Solution
1. Write the address range in binary
2. Separate the fixed part of address
3. Design the logic circuit.

a8 a7 a6 a5 a4 a3 a2 a1 a0
a11 a10 a9 a8
a11 a8
a9
From address 300H  0 0 1 1 0 0 0 0 0 0 0 0 a10 CS
a11
To address 3FFH  001111111111

An easy way of
designing

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 Inside the CPU
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• PC (Program Counter)
• Instruction decoder
• ALU (Arithmetic Logic Unit)
• Registers

PC A
ALU B

CPU C
D
Instruction decoder registers

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 How computers work 0 31h
31
1 C4h A [17]
26h BA
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2
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3 81h A  [6]
4 EAh AA+B
5 0h [7]A
6 5h
7

Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 10 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

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 How computers work 0 31h
1 C4h A [17]
26h BA
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2
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3 81h A  [6]
4 EAh AA+B
5 0h [7]A
6 5h
7

Logic circuit
Address bus 17

Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 1 C 9

D I/O 16 I/O 17 I/O 18 I/O n

Inst. Dec. registers

31

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 How computers work 0 31h
1 C4h
C4 A [17]
26h BA
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2
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3 81h A  [6]
4 EAh AA+B
5 0h [7]A
6 5h
5
7

Logic circuit
Address bus 17
6

Data bus
Write
Control bus Read

ALU
CPU 9
A
B
PC: 1
2
3 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

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 How computers work 0 31h
1 C4h A [17]
26h BA
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2
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3 81h
81 A  [6]
4 EAh
EA
AA+B
5 0h [7]A
6 5h
7

7 Logic circuit
Address bus
Eh
Data bus
Write
Control bus Read

+E
ALU
CPU A
9
B
E
5

PC: 4
35 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

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 How Instruction decoder works
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Opcode Operand Opcode Operand

Instruction

Instruction

Operation Code Meaning

000 Ax
0011 0001 0 31h
1100 0100 1 C4h A [17] 001 A  [x]
0010 0110 2 26h BA 010 A  A – register (x)
1000 0001 3 81h A  [6]
1110 1010 4 EAh AA+B 011 AA+x
0000 0000 5 0h [7]A
0000 0101
100 A  A + register (x)
6 5h
7 101 AA–x
110 Register (xH)  Register (xL)
111 [x]  A

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 Von Neumann vs. Harvard architecture
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Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus

• Harvard architecture

Code Data
Memory Memory

Data bus
CPU Address bus
Control bus

• Von Neumann architecture

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