Lecture-2 20/4/22 10:09 AM

Chapter Introduction
(5 Minutes)

• Diffusion and Ion implantation

• Growth and deposition of dielectric layer: Today’s lecture (35 Minutes)
Thermal oxidation
• Diffusion and Ion implantation
CVD
• Growth and deposition of dielectric layer: Review questions
Plasma CVD ( 5 Min)
Sputtering
Silicon Nitride growth
Introduction to semiconductor Characterisation
tools
EEE 4227 : Processing and fabrication Technology
FM=75 ; 3 Credits ; Exam: 26.25 /Each Section
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Book: Microchip Fabrication: A Practical guide to
Semiconductor Processing by Peter Van Zant
 Diffusion 20/4/22 10:09 AM

diffusion phenomenon takes place when a doped wafer is exposed to a

concentration of atoms higher than the concentration in the wafer. This is
called solid state diffusion.
Formation of doped region and junction by doping 20/4/22 10:09 AM

Dopant amounts and level conductivity type.

 Goals of solid-state diffusion 20/4/22 10:09 AM

The goals of a diffusion process, thermal diffusion or ion-implantation, are threefold:

1. The creation of a specific number (concentration) of dopant atoms in the wafer surface

2. To create an N-P (or P-N) junction at a specific distance below the wafer surface

3. To create a specific distribution and concentration of dopant atoms in the wafer surface
Lateral Diffusion 20/4/22 10:09 AM
Same type diffusion 20/4/22 10:09 AM
 Concentration versus depth graphs and location of junction 20/4/22 10:09 AM

b) P-type dopant, and (c) N-type and P- type dopant.

 Diffusion process 20/4/22 10:09 AM

solid-state thermal diffusion

• Deposition
• Drive-in oxidation
 Deposition process control 20/4/22 10:09 AM

A deposition process is controlled by two factors:

• Diffusivity
• Solubility

Diffusivity is the rate (speed) of movement of the dopant through the particular wafer material.
Diffusivity increases with temperature.

Another factor is the maximum solid solubility of the dopant in the wafer material.
It is the maximum concentration of a specific dopant that can be put into the wafer.
The maximum solid solubility limit increases with increasing temperature.
 Deposition steps and dopant source 20/4/22 10:09 AM

A deposition process requires four steps:

1.Preclean and etch
2.Tube deposition
Dopant sources Liquid sources. Liquid sources of dopants are
3.Deglaze chlorinated or bromi- nated compounds of the desired
• liquid
4.Evaluation element. Thus, a boron liquid source is boron tribromide
• gaseous (BBr3) and a phosphorus liquid source is phospho- rus
• solid states oxychloride (POCl3).
 Deposition from gas source 20/4/22 10:09 AM

Gas sources. Many wafer manufacturers prefer gas dopant sources.

These are hydrated forms of the dopant atom such as arsine (AsH 3
and diborane (B2H6).

advantage:
precise control through pressure regulators and are favored for
deposition on larger-diameter wafers.
The processes are in general cleaner, since the pressurized sources
last longer than liquid sources.
Disadvantage:
unwanted chemical reactions in the manifold can create silica dust
that can contaminate the tube and wafers

Gas source manifold.

 Solid Source for deposition 20/4/22 10:09 AM

Less uniformity and used in discrete components

Large production

High uniformity

Less production due to slugs occupation

Solid source. (a) Remote furnace and (b) neighbour source.

 Drive-in oxidation 20/4/22 10:09 AM

The purpose of this step is twofold:

• redistribution of the dopant in the wafer
• growth of a new oxide on the exposed silicon surface.
 Effect of oxidation 20/4/22 10:09 AM

Pile-up and depletion of dopants during oxidation. (a) Pile-up of N-type

dopants and (b) depletion of P-type dopants.
 Limitation of Thermal deposition 20/4/22 10:09 AM

Limitations of thermal diffusion: At the 0.18-μm design rule level, junctions will be in the 40 nm range;
lateral diffusion at the sub-0.10 μm range, they will be in the 20-nm range.

Wider junctions
Gate regions with dopant concentrations below 1015 atoms/cm2
poor doping control
are required for efficient MOS transistors.
surface contamination interference
dislocation generation
 Ion Implantation 20/4/22 10:09 AM

Ion implantation overcomes these limits of diffusion and also adds additional benefits.
• No side diffusion
• Room temperature diffusion
• Dopants travel deeper in the wafer (reduce surface contamination)
• Wide range of doping concentration
• Greater control of dopants location and number
• photoresist and thin metal layers can be used as doping barriers along with the usual silicon dioxide layers

Ion implantation is a physical process

 Ion Implantation system 20/4/22 10:09 AM
1. Implant sources : Only Gas and solid source

2. Ionization chamber : Dopants are ionised

0.2 to 2.5 MeV

Ion implantation.
(a) Block diagram of ion implanter and
(b) distribution of implanted atoms in wafers. Ion species of BF3.
 Ion Implantation system 20/4/22 10:09 AM

3. Mass analyzing/ion selection 5. Wafer charging

Methods used to neutralize or reduce the charge are

flood guns specifically designed to provide electrons

6. Beam focus

7. Neutral beam trap

Despite the vacuum removal of the majority of the air in the

Analyzing magnet. system, there are still some residual gas molecules in the vicinity of
the ion beam. Collisions between the ions and the residual gas
4. Acceleration tube atoms result in a neutralization of the dopant ion.

Voltages range from 5 to 10 keV

for low-energy implanters
to 0.2 to 2.5 MeV (million electron volts)
for high-energy implanters.
 Ion Implantation system 20/4/22 10:09 AM

8. Beam scanning
 Dopant Concentration in Implanted Regions 20/4/22 10:09 AM

The number of atoms (dose) implanted depends on:

• the beam current density (ions per square centimeter)
• the implant time

The location of the ions in the wafer depends on:

the incoming energy of the ions
the orientation of the wafer
the stopping mechanism of the ion

Within the wafer, the ions are slowed and stopped

by two mechanisms
• The positive ions are slowed by electronic interactions with
the negatively charged electrons in the crystal.
• The other interaction is the physical collision with the Dopant concentration profile after an ion implant.

nucleus of the wafer atoms.

 Crystal damage 20/4/22 10:09 AM

There are three types of damage:

1. lattice damage
2. damage cluster
3. vacancy-interstitial

Lattice damage occurs when the ions collide with host atoms and displace them from their lattice site.

A damage cluster occurs when displaced atoms in turn displace other substrate atoms, creating a cluster of displaced
atoms.

This defect comes about when an incoming ion knocks a substrate atom from a lattice site and the displaced atom comes to
rest in a nonlattice position (shown below)
 Annealing and dopant activation 20/4/22 10:09 AM

The temperature of the anneal is below the diffusion temperature of the dopant to prevent lateral diffusion. A typical anneal in a
tube furnace will take place between 600 and 1000°C in a hydrogen atmosphere

RTP techniques are also used for post-implant annealing. RTP offers fast surface heating that restores the damage without
the substrate temperature rising to the diffusion level. Additionally, the anneal can take place in seconds, whereas a tube
process takes 15 to 30 min
 Uses of Ion Implantation 20/4/22 10:09 AM

e greater control and lack of side diffusion make it the preferred doping technique for dense and small-feature-size circuits.
A predeposition application in CMOS devices is the creation of the deep P-type wells, called retrograde wells, using high-energy imp

• One of the most important uses of ion implantation is for MOS gate threshold adjustment

The threshold voltage is very sensitive to the dopant concentration in the wafer surface under the gate. Ion implantation is
used to create the required dopant concentration in the gate region

• In bipolar technology, ion implantation is used to create

all of the various transistor parts.

• Resistors for both MOS and bipolar circuits are

good candidates for ion implantation.

Ion doping of MOS gate region.

 Advantages of ion implantation 20/4/22 10:09 AM

The benefits include:

▪ Precise dose control from 1010 to 1016 atoms/cm2

▪ Uniform doping of large areas

▪ Dopant profile control through energy selection

▪ Relative ease of implanting all dopant elements

▪ Minimal side diffusion

▪ Implanting of nondopant atoms

▪ Can dope through surface layers

▪ Choice of dopant barriers for selective doping

▪ Tailored doping profiles in deep (retrograde) wells

 Growth and deposition of dielectric layers: 20/4/22 10:09 AM

• Thermal oxidation
• CVD
• plasma CVD
• sputtering
• silicon-nitride growth

Thermal Oxidation Mechanisms

Reaction of silicon and oxygen to form silicon dioxide.

Oxidation temperatures are between 900 and 1200°C

 Thermal Oxidation for oxide layer deposition 20/4/22 10:09 AM

Use of water steam for fast oxidation after 1000

1000 Hydroxyl ions Diffuse through initially grown oxide layer

much faster than oxygen

>1000

Silicon dioxide growth states.

(a) Initial, (b) linear, and (c) parabolic.

Silicon dioxide thickness versus time and temperature in (a) dry oxygen and (b) steam.
 Influences on the oxidation rate 20/4/22 10:09 AM
Wafer orientation
Wafer dopant redistribution
Oxide impurities
Oxidation of polysilicon
Differential oxidation rates and oxide steps

Wafer orientation
á111ñ planes have more silicon atoms than á100ñ planes
The larger number of atoms allows for a faster oxide growth on á111ñ-oriented wafers than for á100ñ-oriented wafers

Wafer dopant redistribution

For example, oxides grown over a highly doped phosphorus layer are less dense than those grown over the other silicon dopants.

The N-type dopants of phosphorus, arsenic, and antimony have a higher solubility in silicon than in silicon dioxide.

the P-type boron, the opposite effect happens. The boron is drawn up into the silicon dioxide layer, causing the silicon at the interface to be depleted of the origin

eral, higher doped regions oxidize faster than more lightly doped regions. Heavily doped phosphorus regions can oxidize 2 to 5 times the undoped oxid
Need for CVD 20/4/22 10:09 AM
Chemical Vapor Deposition Basics 20/4/22 10:09 AM
Chemical Vapor Deposition Basics 20/4/22 10:09 AM
 Low pressure Chemical Vapor Deposition (LPCVD) 20/4/22 10:09 AM

Why LPCVD?
A factor influencing film uniformity and step coverage is the mean free path of the molecules in the reaction
chamber.
The longer the mean free path, the higher the uniformity of the film deposition
Lowering the pressure in the chamber increases the mean free path and the film uniformity.
Decreasing the pressure also allows a lowering of the deposition temperature

LPCVD system advantages includes:

■ Lower chemical reaction temperature

■ Good step coverage and uniformity
■ Vertical loading of wafers for increased productivity and lower exposure to particles
■ Less dependence on gas flow dynamics
■ Less time for gas phase reaction particles to form
■ Can be performed in standard tube furnaces

Disadvantage: A vacuum pump must be added to the system to reduce the pressure in the chamber
 Plasma-enhanced CVD (PECVD) 20/4/22 10:09 AM

A thermal silicon dioxide deposition temperature of approximately 660°C causes unacceptable alloying of aluminum
interconnects into the silicon surface

Replacement of silicon dioxide passivation layers with silicon nitride led to the development of plasma enhanced
(PECV) techniques.

A solution to this problem was a plasma enhancement of the deposition energy.

The increased energy allows a temperature under the 450°C maximum level for deposition over aluminum layers

The combination of low pressure and lower temperatures provides good film uniformity and throughput.

PECVD reactors have the capability of also using the plasma for etching and cleaning the wafer prior to the
deposition step.

This in situ cleaning prepares the deposition surface, eliminating the problem of added contamination picked up
during the loading step
Chemical Vapor Deposition Basics 20/4/22 10:09 AM
Chemical Vapor Deposition Basics 20/4/22 10:09 AM
Epitaxial film doping 20/4/22 10:09 AM
Cell 20/4/22 10:09 AM