Computer For Future Devices Final ST Thomas July 7 2011

Computer for Future Devices:
Embedded Computer Systems
Dr. Amlan Chakrabarti

Reader , School of Information Technology
University of Calcutta, India
acakcs@caluniv.ac.in
1
Introductory Concepts
• Embedded systems overview

– What are they?
• Design challenge – optimizing design metrics
• Technologies
– Processor technologies
– IC technologies
– Design technologies
acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 2

2011
Embedded systems overview
• Computing systems are everywhere

• Most of us think of “desktop” computers
– PC’s
– Laptops
– Mainframes
– Servers
• But there’s another type of computing system
– Far more common...

2011
Embedded systems overview
• Embedded computing systems

Computers are in here...
– Computing systems embedded within
electronic devices and here...
– Hard to define. Nearly any computing and even here...

system other than a desktop computer
– Billions of units produced yearly,
versus millions of desktop units
– Perhaps 50 per household and per
automobile Lots more of these,
though they cost a lot
less each.

2011
A “short list” of embedded systems
Anti-lock brakes Modems
Auto-focus cameras MPEG decoders
Automatic teller machines Network cards
Automatic toll systems Network switches/routers
Automatic transmission On-board navigation
Avionic systems Pagers
Battery chargers Photocopiers
Camcorders Point-of-sale systems
Cell phones Portable video games
Cell-phone base stations Printers
Cordless phones Satellite phones
Cruise control Scanners
Curbside check-in systems Smart ovens/dishwashers
Digital cameras Speech recognizers
Disk drives Stereo systems
Electronic card readers Teleconferencing systems
Electronic instruments Televisions
Electronic toys/games Temperature controllers
Factory control Theft tracking systems
Fax machines TV set-top boxes
Fingerprint identifiers VCR’s, DVD players
Home security systems Video game consoles
Life-support systems Video phones
Medical testing systems Washers and dryers
And the list goes on and on

2011
Some common characteristics of embedded
systems
• Single-functioned
– Executes a single program, repeatedly
• Tightly-constrained
– Low cost, low power, small, fast, etc.
• Reactive and real-time
– Continually reacts to changes in the system’s environment
– Must compute certain results in real-time without delay

2011
An embedded system example -- a digital
camera
Digital camera chip
CCD
CCD preprocessor Pixel coprocessor D2A

A2D
lens
JPEG codec Microcontroller Multiplier/Accum
DMA controller Display ctrl
Memory controller ISA bus interface UART LCD ctrl
• Single-functioned -- always a digital camera

• Tightly-constrained -- Low cost, low power, small, fast
• Reactive and real-time -- only to a small extent

2011
Design challenge – optimizing design metrics
• Obvious design goal:

– Construct an implementation with desired functionality
• Key design challenge:
– Simultaneously optimize numerous design metrics
• Design metric
– A measurable feature of a system’s implementation
– Optimizing design metrics is a key challenge

2011
Design challenge – optimizing design metrics
• Common metrics
– Time-to-prototype: the time needed to build a working version of the
system
– Time-to-market: the time required to develop a system to the point that it
can be released and sold to customers
– Maintainability: the ability to modify the system after its initial release
– Correctness, safety, many more

2011
The performance design metric
• Widely-used measure of system, widely-abused
– Clock frequency, instructions per second – not good measures
– Digital camera example – a user cares about how fast it processes images, not
clock speed or instructions per second
• Latency (response time)
– Time between task start and end
– e.g., Camera’s A and B process images in 0.25 seconds
• Throughput
– Tasks per second, e.g. Camera A processes 4 images per second
– Throughput can be more than latency seems to imply due to concurrency, e.g.
Camera B may process 8 images per second (by capturing a new image while
previous image is being stored).
• Speedup of B over S = B’s performance / A’s performance
– Throughput speedup = 8/4 = 2

2011
Three key embedded system technologies
• Technology
– A manner of accomplishing a task, especially using
technical processes, methods, or knowledge
• Three key technologies for embedded systems
– Processor technology
– IC technology
– Design technology

2011
Processor technology
• The architecture of the computation engine used to implement a
system’s desired functionality
• Processor does not have to be programmable
– “Processor” not equal to general-purpose processor
Controller Datapath Controller Datapath Controller Datapath
Control index
Control Register Control logic Registers
logic
logic and file and State total
State register register State
Custom +
ALU register
General
IR PC ALU IR PC
Data Data
memory memory
Program Data Program memory
memory memory
Assembly code Assembly code
for: for:
total = 0 total = 0
for i =1 to … for i =1 to …
General-purpose (“software”) Application-specific Single-purpose (“hardware”)

2011
Processor technology
• Processors vary in their customization for the problem at hand
total = 0
for i = 1 to N loop
total += M[i]
end loop
Desired
functionality
General-purpose Application-specific Single-purpose

processor processor processor

2011
General-purpose processors
• Programmable device used in a variety of
Controller Datapath
applications
Control
– Also known as “microprocessor” logic and
Register
file
• Features State
register
– Program memory General
– General datapath with large register file and IR PC ALU
general ALU
• User benefits Program
memory
Data
memory
– Low time-to-market and NRE costs
Assembly code
– High flexibility for:
• “Pentium” the most well-known, but total = 0

for i =1 to …
there are hundreds of others

2011
Single-purpose processors
• Digital circuit designed to execute exactly Controller Datapath

one program Control index
logic
– coprocessor, accelerator or peripheral
total
• Features State
register +
– Contains only the components needed to
execute a single program Data
– No program memory memory
• Benefits
– Fast
– Low power
– Small size

2011
Application-specific processors
• Programmable processor optimized for a Controller Datapath
particular class of applications having Control Registers

logic and
common characteristics State
register
– Compromise between general-purpose and Custom
ALU
single-purpose processors IR PC
• Features Data
Program memory
– Program memory memory
– Optimized datapath
Assembly code
– Special functional units for:
• Benefits total = 0
for i =1 to …
– Some flexibility, good performance, size and
power

2011
IC technology
• The manner in which a digital (gate-level)

implementation is mapped onto an IC
– IC: Integrated circuit, or “chip”
– IC technologies differ in their customization to a design
– IC’s consist of numerous layers (perhaps 10 or more)
• IC technologies differ with respect to who builds each layer and
when
gate
IC package IC oxide
source channel drain
Silicon substrate

2011
IC technology
• Three types of IC technologies

– Full-custom/VLSI
– Semi-custom ASIC (gate array and standard cell)
– PLD (Programmable Logic Device)

2011
Full-custom/VLSI
• All layers are optimized for an embedded system’s

particular digital implementation
– Placing transistors
– Sizing transistors
– Routing wires
• Benefits
– Excellent performance, small size, low power
• Drawbacks
– High NRE cost (e.g., $300k), long time-to-market

2011
Semi-custom
• Lower layers are fully or partially built

– Designers are left with routing of wires and maybe placing
some blocks
• Benefits
– Good performance, good size, less NRE cost than a full-
custom implementation (perhaps $10k to $100k)
• Drawbacks
– Still require weeks to months to develop

2011
PLD (Programmable Logic Device)
• All layers already exist

– Designers can purchase an IC
– Connections on the IC are either created or destroyed to
implement desired functionality
– Field-Programmable Gate Array (FPGA) very popular
• Benefits
– Low NRE costs, almost instant IC availability
• Drawbacks
– Bigger, expensive (perhaps $30 per unit), power hungry,
slower
2011
Design Technology
• The manner in which we convert our concept of

desired system functionality into an implementation
Compilation/ Libraries/ Test/
Synthesis IP Verification
System System Hw/Sw/ Model simulat./

Compilation/Synthesis: specification synthesis OS checkers
Automates exploration and
insertion of implementation
details for lower level.
Behavioral Behavior Cores Hw-Sw
specification synthesis cosimulators
Libraries/IP: Incorporates pre-
designed implementation from
lower abstraction level into
higher level. RT RT RT HDL simulators
specification synthesis components
Test/Verification: Ensures correct

functionality at each level, thus
reducing costly iterations Logic Logic Gates/ Gate
between levels. specification synthesis Cells simulators
To final implementation

2011
The co-design ladder
• In the past: Sequential program code (e.g., C, VHDL)
– Hardware and software Compilers

Behavioral synthesis
(1990's)
(1960's,1970's)
design technologies were
Register transfers
very different Assembly instructions RT synthesis
– Recent maturation of Assemblers, linkers
(1980's, 1990's)
synthesis enables a unified (1950's, 1960's) Logic equations / FSM's

Logic synthesis
view of hardware and (1970's, 1980's)
Machine instructions
software Logic gates
• Hardware/software
Implementation
“codesign” Microprocessor plus
program bits: “software”
VLSI, ASIC, or PLD
implementation: “hardware”
The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement.

2011
Independence of processor and IC
technologies
• Basic tradeoff
– General vs. custom
– With respect to processor technology or IC technology
– The two technologies are independent
General- Single-
purpose ASIP purpose
General, processor processor Customized,
providing improved: providing improved:
Flexibility Power efficiency

Maintainability Performance
NRE cost Size
Time- to-prototype Cost (high volume)
Time-to-market
Cost (low volume)
PLD Semi-custom Full-custom

2011
2011
Processor Architectures

2011
Microprocessor Based Systems
• Microprocessor-based systems are electrical systems consisting of
microprocessors, memories, I/O units, and other peripherals.
• Microprocessors are the brains of the systems
• Microprocessors access memories and other units through buses
• The operations of microprocessors are controlled by instructions stored in
memories

2011
Inside the Microprocessor
• A microprocessor is a processor (or Central Processing Unit, CPU)
fabricated on a single integrated circuit.

2011
Evolution of Intel Microprocessors

2011
Other Common Commercial μPs
• PowerPC (IBM, Motorola)

• Athlon, Dulon, Hammer (AMD)
• Crusoe (Transmeta)
• SPARC, UltraSPARC (Sun Microsystems)
• TI’s TMS DSP chips (Texas Instruments)
• StarCore (Motorola, Agere)
• ARM cores (Advanced RISC Machines)
• MIPS cores (MIPS Technologies)

2011
Micro controllers
• A microcontroller is a simple computer implemented in a single VLSI chip.
• In general, microcontrollers are cheap and have low performance
• Microcontrollers are widely used as a processing hardware for specific
target application and so they are very commonly used in Embedded
Applications

2011
ASICs
• Microprocessors are embedded into ASIC chips to implement complex functions
• In general, it requires that the microprocessors have low power consumption and take
small silicon area

2011
2011
Putting Pieces Together

2011
Basic concepts of Memory
• Stores large number of bits

• Memories are organized in words
• An M x N memory
– M=2k words
• k address input signals
– N bits per word
• E.g.: 4096 x 8 memory:
– 4,096 x 8 = 32,768 bits
– 4,096 = 212
• 12 address input signals
• 8 input/output data signals

2011
Memory Access
• Memory access signals

– r/w Selects read or write
– enable Read or write only when asserted
• Memory address/data
– A[0..k-1] Address
– D[0..N-1] Data

2011
Memory classification
• Traditional ROM/RAM distinctions
– ROM: Read only, bits stored without power
– RAM: Read and write, lose stored bits without power
• Traditional distinctions blurred
– Advanced ROMs can be written to
• PROM, EPROM, E2PROM, FLASH
– Advanced RAMs can hold bits without power
• NVRAM
• Writing
– Manner and speed a memory can be written
• Storage
– Ability to hold stored bits once written

2011
Memory Composition (1)
• Wider words (more bits per word)

2011
Memory Composition (2)
• Wider addressing space (more words)

2011
Memory Hierarchy
• Registers & L1 Cache

– Small, very expensive,very fast
• L2 Cache
– Larger, expensive, very fast
• Main memory
– Large, inexpensive, slower
• Disk
– Very large, inexpensive, slow
• Tape
– Largest, inexpensive, sequential access

2011
Interfacing
• Interfacing basics
• Microprocessor interfacing
– I/O Addressing
– Interrupts
– Direct memory access
• Arbitration
• Hierarchical buses
• Protocols
– Serial
– Parallel
– Wireless

2011
A simple bus
• Wires:
– Uni-directional or bi-directional
– One line may represent multiple wires
• Bus Processor
rd'/wr
Memory
enable
– Set of wires with a single function addr[0-11]
• Address bus, data bus data[0-7]
– Or, entire collection of wires

bus
• Address, data and control bus structure
• Associated protocol: rules for

communication

2011
Ports
Processor rd'/wr Memory
port enable
addr[0-11]
data[0-7]
bus
• Conducting device on periphery
• Connects bus to processor or memory
• Often referred to as a pin
– Actual pins on periphery of IC package that plug into socket on printed-circuit board
– Sometimes metallic balls instead of pins
– Today, metal “pads” connecting processors and memories within single IC
• Single wire or set of wires with single function
– E.g., 12-wire address port

2011
Timing Diagrams
• Most common method for describing a rd'/wr
communication protocol enable
• Time proceeds to the right on x-axis
addr
• Control signal: low or high
– May be active low (e.g., go’, /go, or go_L) data
– Use terms assert (active) and deassert
tsetup tread
– Asserting go’ means go=0
read protocol
• Data signal: not valid or valid
• Protocol may have subprotocols rd'/wr
– Called bus cycle, e.g., read and write
enable
– Each may be several clock cycles
addr
• Read example
– rd’/wr set low,address placed on addr for at data
least tsetup time before enable asserted, enable
triggers memory to place data on data wires tsetup twrite
by time tread write protocol

2011
Basic protocol concepts
• Actor: master initiates, servant (slave) respond
• Direction: sender, receiver
• Addresses: special kind of data
– Specifies a location in memory, a peripheral, or a register within a peripheral
• Time multiplexing
– Share a single set of wires for multiple pieces of data
– Saves wires at expense of time
Time-multiplexed data transfer
Master req Servant Master req Servant
data(15:0) data(15:0)
addr data addr data
mux demux mux demux

data(8) addr/data
req req
data 15:8 7:0 addr/data addr data
data serializing address/data muxing

2011
Basic protocol concepts: control methods
Master Servant Master req Servant

req
ack
data
data
req 1 3 req 1 3
ack 2 4
data 2 4
data
taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant puts data on bus and asserts ack
3. Master receives data and deasserts req 3. Master receives data and deasserts req
4. Servant ready for next request 4. Servant ready for next request
Strobe protocol Handshake protocol

2011
Microprocessor interfacing: interrupts
• Suppose a peripheral intermittently receives data,

which must be serviced by the processor
– The processor can poll the peripheral regularly to see if data
has arrived – wasteful
– The peripheral can interrupt the processor when it has data
• Requires an extra pin or pins: Int
– If Int is 1, processor suspends current program, jumps to an
Interrupt Service Routine, or ISR
– Known as interrupt-driven I/O
– Essentially, “polling” of the interrupt pin is built-into the
hardware, so no extra time!

2011
Microprocessor interfacing: interrupts
• What is the address (interrupt address vector) of the
ISR?
– Fixed interrupt
• Address built into microprocessor, cannot be changed
• Either ISR stored at address or a jump to actual ISR stored if not
enough bytes available
– Vectored interrupt
• Peripheral must provide the address
• Common when microprocessor has multiple peripherals connected
by a system bus
– Compromise: interrupt address table

2011
Interrupt-driven I/O using fixed ISR location
Time 1(a): μP is executing its main program. 1(b): P1 receives input data in a
register with address 0x8000.
2: P1 asserts Int to request

servicing by the
3: After completing instruction at 100, μP microprocessor.
sees Int asserted, saves the PC’s value of
100, and sets PC to the ISR fixed location
of 16.
4(a): The ISR reads data from 0x8000, 4(b): After being read, P1 de-
modifies the data, and writes the resulting asserts Int.
data to 0x8001.
5: The ISR returns, thus restoring PC to

100+1=101, where μP resumes executing.

2011
1(a): P is executing its main program Program memory μP Data memory

ISR
1(b): P1 receives input data in a register 16: MOV R0, 0x8000
17: # modifies R0 System bus
with address 0x8000.
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction

2011
2: P1 asserts Int to request servicing by Program memory μP Data memory

the microprocessor ISR
16: MOV R0, 0x8000
18: MOV 0x8001, R0
... Int P1 P2
Main program 1
... PC 0x8000 0x8001
100: instruction
101: instruction

2011
3: After completing instruction at 100, Program memory μP Data memory

P sees Int asserted, saves the PC’s ISR
value of 100, and sets PC to the ISR 16: MOV R0, 0x8000
fixed location of 16.
18: MOV 0x8001, R0
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction 100

2011
4(a): The ISR reads data from 0x8000, Program memory μP Data memory
modifies the data, and writes the ISR
resulting data to 0x8001. 16: MOV R0, 0x8000
4(b): After being read, P1 deasserts Int. 18: MOV 0x8001, R0
... Int P1 P2
Main program 0
... PC 0x8000 0x8001
100: instruction

2011
5: The ISR returns, thus restoring PC to Program memory μP Data memory

100+1=101, where P resumes ISR
executing. 16: MOV R0, 0x8000
18: MOV 0x8001, R0
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction +1

2011
Interrupt-driven I/O using vectored interrupt
1(a): μP is executing its main program. 1(b): P1 receives input data in a

Time
register with address 0x8000.
2: P1 asserts Int to request servicing

3: After completing instruction at 100, μP sees Int by the microprocessor.
asserted, saves the PC’s value of 100, and asserts
Inta.
4: P1 detects Inta and puts interrupt
address vector 16 on the data bus.
5(a): μP jumps to the address on the bus (16).

The ISR there reads data from 0x8000, modifies
the data, and writes the resulting data to 0x8001. 5(b): After being read, P1 deasserts
Int.
6: The ISR returns, thus restoring PC to

100+1=101, where μP resumes executing.

2011
1(a): P is executing its main program Program memory μP Data memory

ISR
with address 0x8000. 17: # modifies R0 System bus
18: MOV 0x8001, R0
... Inta P1 P2
Main program Int
... PC 16
100: instruction 0x8000 0x8001

2011
2: P1 asserts Int to request servicing by the Program memory μP Data memory

microprocessor ISR
16: MOV R0, 0x8000
18: MOV 0x8001, R0
... Inta P1 P2
Main program Int
... PC 1 16

2011
3: After completing instruction at 100, μP Program memory μP Data memory

sees Int asserted, saves the PC’s value of ISR
100, and asserts Inta 16: MOV R0, 0x8000
18: MOV 0x8001, R0
19: RETI # ISR return 1
... Inta P1 P2
Main program Int
... PC 16

2011
4: P1 detects Inta and puts interrupt Program memory μP Data memory

address vector 16 on the data bus ISR
16: MOV R0, 0x8000
17: # modifies R0 16 System bus
18: MOV 0x8001, R0
... Inta P1 P2
Main program Int
... PC 16

2011
5(a): PC jumps to the address on the bus Program memory μP Data memory
(16). The ISR there reads data from ISR
0x8000, modifies the data, and writes the 16: MOV R0, 0x8000
resulting data to 0x8001.
18: MOV 0x8001, R0
... Inta P1 P2
5(b): After being read, P1 deasserts Int. Int
Main program
... PC 0 16

2011
6: The ISR returns, thus restoring the PC Program memory μP Data memory
to 100+1=101, where the μP resumes ISR
16: MOV R0, 0x8000
18: MOV 0x8001, R0
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction +1

2011
Interrupt address table
• Compromise between fixed and vectored interrupts

– One interrupt pin
– Table in memory holding ISR addresses (maybe 256 words)
– Peripheral doesn’t provide ISR address, but rather index into
table
• Fewer bits are sent by the peripheral
• Can move ISR location without changing peripheral

2011
Additional interrupt issues
• Maskable vs. non-maskable interrupts
– Maskable: programmer can set bit that causes processor to ignore
interrupt
• Important when in the middle of time-critical code
– Non-maskable: a separate interrupt pin that can’t be masked
• Typically reserved for drastic situations, like power failure requiring
immediate backup of data to non-volatile memory
• Jump to ISR
– Some microprocessors treat jump same as call of any subroutine
• Complete state saved (PC, registers) – may take hundreds of cycles
– Others only save partial state, like PC only
• Thus, ISR must not modify registers, or else must save them first
• Assembly-language programmer must be aware of which registers stored

2011
Direct memory access
• Buffering
– Temporarily storing data in memory before processing
– Data accumulated in peripherals commonly buffered
• Microprocessor could handle this with ISR
– Storing and restoring microprocessor state inefficient
– Regular program must wait
• DMA controller more efficient
– Separate single-purpose processor
– Microprocessor relinquishes control of system bus to DMA controller
– Microprocessor can meanwhile execute its regular program
• No inefficient storing and restoring state due to ISR call
• Regular program need not wait unless it requires the system bus
– Harvard archictecture – processor can fetch and execute instructions as long as they
don’t access data memory – if they do, processor stalls

2011
Peripheral to memory transfer without DMA,
using vectored interrupt
1(a): μP is executing its main program. 1(b): P1 receives input data in a register
Time
2: P1 asserts Int to request servicing by

the microprocessor.
3: After completing instruction at 100, μP sees Int
asserted, saves the PC’s value of 100, and asserts Inta.
4: P1 detects Inta and puts interrupt
address vector 16 on the data bus.
5(a): μP jumps to the address on the bus (16). The ISR

there reads data from 0x8000 and then writes it to
0x0001, which is in memory. 5(b): After being read, P1 deasserts Int.
6: The ISR returns, thus restoring PC to 100+1=101,

where μP resumes executing.

2011
1(a): P is executing its main program Program memory μP Data memory
ISR 0x0000 0x0001
17: # modifies R0
18: MOV 0x0001, R0 System bus
...
Main program Inta P1
...
Int
100: instruction 16
101: instruction PC
0x8000

2011
2: P1 asserts Int to request servicing by the Program memory μP Data memory
microprocessor ISR 0x0000 0x0001
16: MOV R0, 0x8000
17: # modifies R0
...
...
Int
100: instruction 16
PC 1
101: instruction 0x8000
100

2011
3: After completing instruction at 100, P Program memory μP Data memory
sees Int asserted, saves the PC’s value of ISR 0x0000 0x0001
100, and asserts Inta. 16: MOV R0, 0x8000
17: # modifies R0
... 1
...
Int
100: instruction 16
101: instruction PC
0x8000
100

2011
using vectored interrupt (cont’)
4: P1 detects Inta and puts interrupt Program memory μP Data memory
address vector 16 on the data bus. ISR 0x0000 0x0001
16: MOV R0, 0x8000
17: # modifies R0
16
...
...
Int
100: instruction 16
101: instruction PC
0x8000
100

2011
5(a): P jumps to the address on the bus Program memory μP Data memory
(16). The ISR there reads data from 0x8000 ISR 0x0000 0x0001
and then writes it to 0x0001, which is in 16: MOV R0, 0x8000
17: # modifies R0
memory.
18: MOV 0x0001,
0x8001, R0 System bus
5(b): After being read, P1 de-asserts Int. ...
...
Int
100: instruction 16
PC 0
100

2011
6: The ISR returns, thus restoring PC to Program memory μP Data memory
100+1=101, where P resumes executing. ISR 0x0000 0x0001
16: MOV R0, 0x8000
17: # modifies R0
18: MOV 0x0001,
0x8001, R0 System bus
...
...
Int
100: instruction 16
101: instruction PC
+1 0x8000
100

2011
Peripheral to memory transfer with DMA
1(a): μP is executing its main program. 1(b): P1 receives input

Time
It has already configured the DMA ctrl data in a register with

registers. address 0x8000.
3: DMA ctrl asserts Dreq

4: After executing instruction 100, μP to request control of
sees Dreq asserted, releases the system system bus. 2: P1 asserts req to request
bus, asserts Dack, and resumes servicing by DMA ctrl.
execution. μP stalls only if it needs the
system bus to continue executing.
5: (a) DMA ctrl asserts
ack (b) reads data from
0x8000 and (b) writes that
data to 0x0001.
6:. DMA de-asserts Dreq

and ack completing
handshake with P1.
7(a): μP de-asserts Dack and resumes 7(b): P1 de-asserts req.
control of the bus.

2011
(cont’)
1(a): P is executing its main program. It has Program memory μP Data memory
already configured the DMA ctrl registers 0x0000 0x0001
No ISR needed!
1(b): P1 receives input data in a register with System bus
address 0x8000.
... Dack
Main program DMA ctrl P1
... Dreq
0x0001 ack
100: instruction PC 0x8000 req
100

2011
(cont’)
2: P1 asserts req to request servicing Program memory μP Data memory
by DMA ctrl. 0x0000 0x0001
No ISR needed!
3: DMA ctrl asserts Dreq to request control of System bus
system bus
... Dack
... Dreq
1 0x0001 ack
100 1

2011
(cont’)
4: After executing instruction 100, P sees Program memory μP Data memory
Dreq asserted, releases the system bus, asserts 0x0000 0x0001
Dack, and resumes execution, P stalls only if No ISR needed!
it needs the system bus to continue executing. System bus
... 1
Dack DMA ctrl P1
Main program Dreq
... 0x0001 ack
100

2011
(cont’)
5: DMA ctrl (a) asserts ack, (b) reads data Program memory μP Data memory
from 0x8000, and (c) writes that data to 0x0000 0x0001
0x0001. No ISR needed!
System bus
(Meanwhile, processor still executing if not
stalled!)
... Dack
... Dreq 1
0x0001 ack
100

2011
(cont’)
6: DMA de-asserts Dreq and ack completing Program memory μP Data memory
the handshake with P1. 0x0000 0x0001
No ISR needed!
System bus
... Dack
... Dreq 0
0 0x0001 ack
100

2011
ISA bus DMA cycles
Processor Memory
ISA-Bus
R A
R
DMA A I/O Device
DMA Memory-Write Bus Cycle DMA Memory-Read Bus Cycle
CYCLE C1 C2 C3 C4 C5 C6 CYCLE C1 C2 C3 C4 C5 C6
C7 C7
CLOCK CLOCK
D[7-0] DATA D[7-0] DATA
A[19-0] ADDRESS A[19-0] ADDRESS
ALE ALE
/IOR /MEMR
/MEMW /IOW
CHRDY CHRDY

2011
Arbitration: Priority arbiter
• Consider the situation where multiple peripherals request service from single
resource (e.g., microprocessor, DMA controller) simultaneously - which
gets serviced first?
• Priority arbiter
– Single-purpose processor
– Peripherals make requests to arbiter, arbiter makes requests to resource
– Arbiter connected to system bus for configuration only
Micro-
processor
System bus 7
Inta 5
Priority Peripheral1 Peripheral2
Int arbiter
3
Ireq1 2 2
Iack1 6
Ireq2
Iack2

2011
Arbitration using a priority arbiter
Micro-
processor
System bus 7
Inta 5
Priority Peripheral1 Peripheral2
Int arbiter
3 2 2
Ireq1
Iack1 6
Ireq2
Iack2
1. 1. Microprocessor is executing its program.

2. 2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2.
3. 3. Priority arbiter sees at least one Ireq input asserted, so asserts Int.
4. 4. Microprocessor stops executing its program and stores its state.
5. 5. Microprocessor asserts Inta.
6. 6. Priority arbiter asserts Iack1 to acknowledge Peripheral1.
7. 7. Peripheral1 puts its interrupt address vector on the system bus
8. 8. Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns
9. (and completes handshake with arbiter).
10. 9. Microprocessor resumes executing its program.

2011
Arbitration: Priority arbiter
• Types of priority
• Fixed priority
– each peripheral has unique rank
– highest rank chosen first with simultaneous requests
– preferred when clear difference in rank between peripherals
• Rotating priority (round-robin)
– priority changed based on history of servicing
– better distribution of servicing especially among peripherals with
similar priority demands

2011
Arbitration: Daisy-chain arbitration
• Arbitration done by peripherals
– Built into peripheral or external logic added
• req input and ack output added to each peripheral
• Peripherals connected to each other in daisy-chain manner
– One peripheral connected to resource, all others connected “upstream”
– Peripheral’s req flows “downstream” to resource, resource’s ack flows “upstream”
to requesting peripheral
– Closest peripheral has highest priority
P
System bus
Peripheral1 Peripheral2
Inta
Ack_in Ack_out Ack_in Ack_out
Int Req_out Req_in Req_out Req_in 0
Daisy-chain aware peripherals

2011
Arbitration: Daisy-chain arbitration
• Pros/cons
– Easy to add/remove peripheral - no system redesign needed
– Does not support rotating priority
– One broken peripheral can cause loss of access to other
peripherals
Micro-
P
processor System bus
System bus
Inta
Priority Peripheral Peripheral Peripheral1 Peripheral2
Int arbiter 1 2 Inta
Ack_in Ack_out Ack_in Ack_out
Ireq1 Int Req_out Req_in Req_out Req_in 0
Iack1
Ireq2
Daisy-chain aware peripherals
Iack2

2011
Multilevel bus architectures
• Don’t want one bus for all communication
– Peripherals would need high-speed, processor-specific bus interface
• excess gates, power consumption, and cost; less portable
– Too many peripherals slows down bus
• Processor-local bus Micro-
processor
Cache Memory
controller
DMA
controller
– High speed, wide, most frequent
communication
– Connects microprocessor, cache, memory Processor-local bus
controllers, etc.
Peripheral Peripheral Peripheral Bridge
• Peripheral bus
– Lower speed, narrower, less frequent
communication
– Typically industry standard bus (ISA, PCI) Peripheral bus
for portability
• Bridge
– Single-purpose processor converts communication between busses

2011
Advanced communication principles
• Layering
– Break complexity of communication protocol into pieces easier to design and
understand
– Lower levels provide services to higher level
• Lower level might work with bits while higher level might work with packets of data
– Physical layer
• Lowest level in hierarchy
• Medium to carry data from one actor (device or node) to another
• Parallel communication
– Physical layer capable of transporting multiple bits of data
• Serial communication
– Physical layer transports one bit of data at a time
• Wireless communication
– No physical connection needed for transport at physical layer

2011
Parallel communication
• Multiple data, control, and possibly power wires

– One bit per wire
• High data throughput with short distances
• Typically used when connecting devices on same IC or same
circuit board
– Bus must be kept short
• long parallel wires result in high capacitance values which requires more
time to charge/discharge
• Data misalignment between wires increases as length increases
• Higher cost, bulky

2011
Serial communication
• Single data wire, possibly also control and power wires

• Words transmitted one bit at a time
• Higher data throughput with long distances
– Less average capacitance, so more bits per unit of time
• Cheaper, less bulky
• More complex interfacing logic and communication protocol
– Sender needs to decompose word into bits
– Receiver needs to recompose bits into word
– Control signals often sent on same wire as data increasing protocol
complexity

2011
Serial protocols: I2C
• I2C (Inter-IC)
– Two-wire serial bus protocol developed by Philips Semiconductors
nearly 20 years ago
– Enables peripheral ICs to communicate using simple communication
hardware
– Data transfer rates up to 100 kbits/s and 7-bit addressing possible in
normal mode
– 3.4 Mbits/s and 10-bit addressing in fast-mode
– Common devices capable of interfacing to I2C bus:
• EPROMS, Flash, and some RAM memory, real-time clocks, watchdog
timers, and microcontrollers

2011
I2C bus structure
SCL
SDA
Micro- EEPROM Temp. LCD-

controller (servant) Sensor controller
(master) (servant) (servant) < 400 pF
Addr=0x01 Addr=0x02 Addr=0x03
SDA SDA SDA SDA
SCL SCL SCL SCL
Start condition Sending 0 Sending 1 Stop condition
From From
Servant receiver
D
C
S A A A A R A D D D A S O
T R 6 5 0 / C 8 7 0 C T P
T w K K
Typical read/write cycle

2011
Serial protocols: CAN
• CAN (Controller area network)
– Protocol for real-time applications
– Developed by Robert Bosch GmbH
– Originally for communication among components of cars
– Applications now using CAN include:
• elevator controllers, copiers, telescopes, production-line control systems, and
medical instruments
– Data transfer rates up to 1 Mbit/s and 11-bit addressing
– Common devices interfacing with CAN:
• 8051-compatible 8592 processor and standalone CAN controllers
– Actual physical design of CAN bus not specified in protocol
• Requires devices to transmit/detect dominant and recessive signals to/from bus
• e.g., ‘1’ = dominant, ‘0’ = recessive if single data wire used
• Bus guarantees dominant signal prevails over recessive signal if asserted simultaneously

2011
Parallel protocols: PCI Bus
• PCI Bus (Peripheral Component Interconnect)

– High performance bus originated at Intel in the early 1990’s
– Standard adopted by industry and administered by PCISIG (PCI Special Interest
Group)
– Interconnects chips, expansion boards, processor memory subsystems
– Data transfer rates of 127.2 to 508.6 Mbits/s and 32-bit addressing
• Later extended to 64-bit while maintaining compatibility with 32-bit schemes
– Synchronous bus architecture
– Multiplexed data/address lines

2011
2011
Describing Behavior

2011
Introduction
• Describing embedded system’s processing behavior

– Can be extremely difficult
• Complexity increasing with increasing IC capacity
– Past: washing machines, small games, etc.
• Hundreds of lines of code
– Today: TV set-top boxes, Cell phone, etc.
• Hundreds of thousands of lines of code
• Desired behavior often not fully understood in beginning
– Many implementation bugs due to description mistakes/omissions
– English (or other natural language) common starting point
• Precise description difficult to impossible
• Example: Motor Vehicle Code – thousands of pages long...

2011
Models and languages
• How can we (precisely) capture behavior?
– We may think of languages (C, C++), but computation model is the key
• Common computation models:
– Sequential program model
• Statements, rules for composing statements, semantics for executing them
– Communicating process model
• Multiple sequential programs running concurrently
– State machine model
• For control dominated systems, monitors control inputs, sets control outputs
– Dataflow model
• For data dominated systems, transforms input data streams into output streams
– Object-oriented model
• For breaking complex software into simpler, well-defined pieces

2011
Introductory example: An elevator controller
Partial English description System interface
• Simple elevator “Move the elevator either up or down Unit up
controller to reach the requested floor. Once at Control down

the requested floor, open the door for open
at least 10 seconds, and keep it open
– Request Resolver until the requested floor changes. floor
resolves various floor Ensure the door is never open while

moving. Don’t change directions
req
Request
requests into single unless there are no higher requests Resolver
b1
buttons
when moving up or no lower requests inside
requested floor when moving down…”
... b2
bN
elevator
– Unit Control moves up1 up/down

up2
elevator to this requested
buttons
dn2 on each
up3 floor
floor dn3
...
• Try capturing in C... dnN

2011
Elevator controller using a sequential
program model
System interface
Sequential program model
Partial English description
Inputs: int floor; bit b1..bN; up1..upN-1; dn2..dnN;
Unit up
Outputs: bit up, down, open;
Global variables: int req; “Move the elevator either up or down Control down
void UnitControl() void RequestResolver() to reach the requested floor. Once at open
{ { the requested floor, open the door for
up = down = 0; open = 1; while (1) floor
while (1) { ...
at least 10 seconds, and keep it open
until the requested floor changes. req
while (req == floor); req = ...
open = 0; ... Ensure the door is never open while Request
if (req > floor) { up = 1;} } Resolver
else {down = 1;}
moving. Don’t change directions b1
buttons
void main()
while (req != floor); unless there are no higher requests b2
inside
{ ... elevator
up = down = 0; Call concurrently: when moving up or no lower requests bN
open = 1;
delay(10);
UnitControl() and when moving down…”
RequestResolver() up1 up/down
} }
} up2 buttons
dn2 on each
up3 floor
dn3
You might have come up with something having ...
even more if statements. dnN

2011
Finite-state machine (FSM) model
• Trying to capture this behavior as sequential program is a bit
awkward
• Instead, we might consider an FSM model, describing the system
as:
– Possible states
• E.g., Idle, GoingUp, GoingDn, DoorOpen
– Possible transitions from one state to another based on input
• E.g., req > floor
– Actions that occur in each state
• E.g., In the GoingUp state, u,d,o,t = 1,0,0,0 (up = 1, down, open, and timer_start =
0)
• Try it...

2011
Finite-state machine (FSM) model
UnitControl process using a state machine
req > floor
u,d,o, t = 1,0,0,0 GoingUp !(req > floor)
req > floor timer < 10

u,d,o,t = 0,0,1,0 !(timer < 10)
Idle DoorOpen
req == floor u,d,o,t = 0,0,1,1
req < floor
u,d,o,t = 0,1,0,0 !(req<floor)

GoingDn
u is up, d is down, o is open

req < floor
t is timer_start

2011
Describing a system as a state machine
1. List all possible states 2. Declare all variables (none in this example)
3. For each state, list possible transitions, with conditions, to other states
4. For each state and/or transition, req > floor
list associated actions
5. For each state, ensure exclusive u,d,o, t = 1,0,0,0 GoingUp !(req > floor)
and complete exiting transition
conditions req > floor timer < 10
u,d,o,t = 0,0,1,0
• No two exiting conditions can Idle !(timer < 10) DoorOpen
be true at same time req == floor
req < floor
u,d,o,t = 0,0,1,1
– Otherwise nondeterministic
state machine u,d,o,t = 0,1,0,0
!(req<floor)
GoingDn
• One condition must be true at
any given time u is up, d is down, o is open
req < floor
– Reducing explicit transitions t is timer_start
should be avoided when first

learning

2011
State machine vs. sequential program model
• Different thought process used with each model
• State machine:
– Encourages designer to think of all possible states and transitions among states
based on all possible input conditions
• Sequential program model:
– Designed to transform data through series of instructions that may be iterated
and conditionally executed
• State machine description excels in many cases
– More natural means of computing in those cases
– Not due to graphical representation (state diagram)
• Would still have same benefits if textual language used (i.e., state table)
• Besides, sequential program model could use graphical representation (i.e., flowchart)

2011
Try Capturing Other Behaviors with an FSM
• E.g., Answering machine blinking light when there are

messages
• E.g., A simple telephone answering machine that
answers after 4 rings when activated
• E.g., A simple crosswalk traffic control light
• Others

2011
Capturing state machines in
sequential programming language
• Despite benefits of state machine model, most popular development tools use
sequential programming language
– C, C++, Java, Ada, VHDL, Verilog, etc.
– Development tools are complex and expensive, therefore not easy to adapt or replace
• Must protect investment
• Two approaches to capturing state machine model with sequential programming
language
– Front-end tool approach
• Additional tool installed to support state machine language
– Graphical and/or textual state machine languages
– May support graphical simulation
– Automatically generate code in sequential programming language that is input to main development tool
• Drawback: must support additional tool (licensing costs, upgrades, training, etc.)
– Language subset approach
• Most common approach...

2011
Language subset approach
• Follow rules (template) for capturing
state machine constructs in equivalent #define IDLE0
#define GOINGUP1
sequential language constructs #define GOINGDN2
#define DOOROPEN3
• Used with software (e.g.,C) and void UnitControl() {
int state = IDLE;
hardware languages (e.g.,VHDL) while (1) {
switch (state) {
• Capturing UnitControl state machine IDLE: up=0; down=0; open=1; timer_start=0;
if (req==floor) {state = IDLE;}
in C if (req > floor) {state = GOINGUP;}
if (req < floor) {state = GOINGDN;}
– Enumerate all states (#define) break;
GOINGUP: up=1; down=0; open=0; timer_start=0;
– Declare state variable initialized to if (req > floor) {state = GOINGUP;}
initial state (IDLE) if (!(req>floor)) {state = DOOROPEN;}
break;
– Single switch statement branches to GOINGDN: up=1; down=0; open=0; timer_start=0;
if (req < floor) {state = GOINGDN;}
current state’s case if (!(req<floor)) {state = DOOROPEN;}
break;
– Each case has actions DOOROPEN: up=0; down=0; open=1; timer_start=1;
• up, down, open, timer_start if (timer < 10) {state = DOOROPEN;}
if (!(timer<10)){state = IDLE;}
– Each case checks transition conditions }
break;
}
to determine next state }
• if(…) {state = …;} UnitControl state machine in sequential programming language

2011
Design Technologies
• Design task
– Define system functionality
– Convert functionality to physical implementation while
• Satisfying constrained metrics
• Optimizing other design metrics
• Designing embedded systems is hard
– Complex functionality
• Millions of possible environment scenarios
• Competing, tightly constrained metrics
– Productivity gap
• As low as 10 lines of code or 100 transistors produced per day

2011
Improving productivity
• Design technologies developed to improve productivity
• We focus on technologies advancing hardware/software unified
view
– Automation Specification
• Program replaces manual design Automation
• Synthesis
– Reuse Verification
Implementation
Reuse
• Predesigned components
• Cores
• General-purpose and single-purpose processors on single IC
– Verification
• Ensuring correctness/completeness of each design step
• Hardware/software co-simulation

2011
2011
Implementation Technologies

2011
Design Styles
Style
Full-custom Standard cell Gate array FPGA
Cell size Variable Fixed height Fixed Fixed
Cell type Variable Variable Fixed Programmable
Cell placement Variable In row Fixed Fixed
Interconnections Variable Variable Variable Programmable
Design cost High Medium Medium Low

2011
Design Styles
Style
Full-custom Standard cell Gate array FPGA
Area Compact Compact to Moderate Large

moderate
Performance High High to Moderate Low

moderate
Fabricate All layers All layers Routing layers No layers

only

2011
Full Custom
• Cell design has no limitation
• Blocks can be placed in any location
• Design has several levels of hierarchy
• Some metal layers are reserved for top level routing
• Width: M4  M3  …
• Via: V3  V2  …
• Interconnect area: dominate
• transistor area: lower bound
• Compact Layout, long development time (uProcessor, performance and
cost sensitive design)
• Term: I/O Pad

2011
Full Custom Design Example
I/O Pad
Via
Data path
Metal2
PLA I/O
Metal1
RAM
Random logic
(standard
A/D cell design)
[©Sherwani]
2011
Standard Cell (Cell Based)
VDD Metal1 Cell Feedthrough GND
Metal2
• Each cell has equal height D C C B

• IC service company provides cell
library (for specific fab. com.): A C C
500 ~ 1200 cells
• Design rule + Abutting rule D C D B
C C C B
Cell 1 Cell 2
Cell library A B
Space/2 C D
2011 Floorplan [©Sherwani]
Standard Cell (Cell Based) (Cont.)
• Each type of cell has several transistor sizes

• What type of design
– Non-hierarchical circuits of moderate size
– Cell synthesis by logic synthesizer
• Cell library development requires enormous
manpower

2011
Gate Arrays
• All cells are identical
– Prefabricated cells on the wafer
Vertical Channel
• Design Process
– Design  a number of identical
blocks
– Blocks  cell assignment
Horizontal channel
problems
– Complete interconnection
between the cells
The number of available tracks in
each channel is fixed
– Fabrication process for routing
layers on the top of the wafer

2011
Gate Arrays (Cont.)
• Benefit
– Low cost: Reduce the number of
masks, increasing yield, simplified
design process
– Simple CAD problems
• Limitation
– Design complexity
– Performance

2011
Field Programmable Gate Arrays
• Cells and interconnect are prefabricated
Programmable
IO Pins or
Logic Block
Feedthrough
Routing
path
Channel
Antifuse
Cross fuse

2011
Field Programmable Gate Arrays (Cont.)
• Design Process
– Decompose a design into several sub-blocks
– Map each sub-block into a logic block
– Program the FPGA interconnects between related logic blocks
– Blow the fuses to break through those interconnects under plan
• Programmable device
– Fuses (once program) or pass-transistor (non-destructive)

2011
2011
Design Technologies

2011
Embedded System
Development Process
• Determine the requirements of the embedded system
• Design the system architecture
• Select the operating system
• Choose the processor and the associated peripherals
• Choose the development platform
• Code the application and optimize the code according to code optimization guidelines
• Verify the software on the host system
• Verify the software on the target system

2011
Automation: synthesis
• Early design mostly hardware
• Software complexity increased with advent
of general-purpose processor The codesign ladder
• Different techniques for software design
and hardware design Sequential program code (e.g., C, VHDL)
– Caused division of the two fields Behavioral synthesis

• Design tools evolve for higher levels of Compilers
(1990s)
abstraction (1960s,1970s)
Register transfers
– Different rate in each field Assembly instructions

RT synthesis
(1980s, 1990s)
• Hardware/software design fields rejoining
Logic equations / FSM's
– Both can start from behavioral description in Assemblers, linkers
sequential program model (1950s, 1960s) Logic synthesis
(1970s, 1980s)
– 30 years longer for hardware design to reach
Machine instructions Logic gates
this step in the ladder
• Many more design dimensions Microprocessor plus Implementation VLSI, ASIC, or PLD
program bits implementation
• Optimization critical

2011
Increasing abstraction level
• Higher abstraction level focus of hardware/software design evolution
– Description smaller/easier to capture
• E.g., Line of sequential program code can translate to 1000 gates
– Many more possible implementations available
• (a) Like flashlight, the higher above the ground, the more ground illuminated
– Sequential program designs may differ in performance/transistor count by orders of magnitude
– Logic-level designs may differ by only power of 2
• (b) Design process proceeds to lower abstraction level, narrowing in on single
implementation modeling cost increases
opportunities decrease
idea idea
back-of-the-envelope
sequential program
register-transfers
logic
implementation implementation
(a) (b)

2011
Synthesis
• Automatically converting system’s behavioral description to a structural
implementation
– Complex whole formed by parts
– Structural implementation must optimize design metrics
• More expensive, complex than compilers
– Cost = $100s to $10,000s
– User controls 100s of synthesis options
– Optimization critical
• Otherwise could use software
– Optimizations different for each user
– Run time = hours, days

2011
Technology mapping
• Library of gates available for implementation

– Simple
• only 2-input AND,OR gates
– Complex
• various-input AND,OR,NAND,NOR,etc. gates
• Efficiently implemented meta-gates (i.e., AND-OR-INVERT,MUX)
• Final structure consists of specified library’s components only
• If technology mapping integrated with logic synthesis
– More efficient circuit
– More complex problem
– Heuristics required

2011
Simulation
• Create computer model of design

– Provide sample input
– Check for acceptable output
• Correctness example
– ALU
• Provide all possible input combinations
• Check outputs for correct results
• Completeness example
– Elevator door closed when moving
• Provide all possible input sequences
• Check door always closed when elevator moving

2011
Emulators
• General physical device system mapped to
– Microprocessor emulator
• Microprocessor IC with some monitoring, control circuitry
– SPP emulator
• FPGAs (10s to 100s)
– Usually supports debugging tasks
• Created to help solve simulation disadvantages
– Mapped relatively quickly
• Hours, days
– Can be placed in real environment
• No environment setup time
• No incomplete environment
– Typically faster than simulation
• Hardware implementation

2011
Reuse: intellectual property cores
• Commercial off-the-shelf (COTS) components
– Predesigned, prepackaged ICs
– Implements GPP or SPP
– Reduces design/debug time
– Have always been available
• System-on-a-chip (SOC)
– All components of system implemented on single chip
– Made possible by increasing IC capacities
– Changing the way COTS components sold
• As intellectual property (IP) rather than actual IC
– Behavioral, structural, or physical descriptions
– Processor-level components known as cores
• SOC built by integrating multiple descriptions

2011
IP protection
• Past
– Illegally copying IC very difficult
• Reverse engineering required tremendous, deliberate effort
• “Accidental” copying not possible
• Today
– Cores sold in electronic format
• Deliberate/accidental unauthorized copying easier
• Safeguards greatly increased
• Contracts to ensure no copying/distributing
• Encryption techniques
– limit actual exposure to IP
• Watermarking
– determines if particular instance of processor was copied
– whether copy authorized

2011
2011
Hardware Software Co-design issues

2011
Hardware/software parallel evolution
• Software design evolution
– Machine instructions
– Assemblers
• convert assembly programs into machine
The codesign ladder
instructions
– Compilers Sequential program code (e.g., C, VHDL)
• translate sequential programs into assembly Behavioral synthesis

(1990s)
• Hardware design evolution Compilers
(1960s,1970s)
– Interconnected logic gates Register transfers
– Logic synthesis Assembly instructions

RT synthesis
(1980s, 1990s)
• converts logic equations or FSMs into gates
Logic equations / FSM's
– Register-transfer (RT) synthesis Assemblers, linkers
Logic synthesis
• converts FSMDs into FSMs, logic equations, (1950s, 1960s)
(1970s, 1980s)
predesigned RT components (registers,
adders, etc.) Machine instructions Logic gates
– Behavioral synthesis Microprocessor plus Implementation VLSI, ASIC, or PLD

program bits implementation
• converts sequential programs into FSMDs

2011
Hardware/software co-simulation
• Variety of simulation approaches exist
– From very detailed
• E.g., gate-level model
– To very abstract
• E.g., instruction-level model
• Simulation tools evolved separately for hardware/software
– Recall separate design evolution
– Software (GPP)
• Typically with instruction-set simulator (ISS)
– Hardware (SPP)
• Typically with models in HDL environment
• Integration of GPP/SPP on single IC creating need for merging
simulation tools
2011
Embedded System Design Flow
System specification
Architecture exploration
Hardware/software partitioning
HW SW
Software
Hardware design compilation

2011
-pro-
ARM DSP
cessor
cessor2
Virtual Architecture exploration

HW ASIC
component
Hardware/software
Within the vast range of implementation partitioning
choices, one has to
find the one that fits the requirements best.
HW SW
• low power
• low cost Hardware
Hardwaredesign
design Software
Requires design libraries. compilation
Important: performance estimates in HW and SW

- processing speed / memory allocation
- silicon area / power dissipation
• Has to be fast / refine gradually.

2011
-pro-
DSP
cessor
Virtual Architecture exploration

HW ASIC
component
Algorithm
{ HW SW
Code 1 Hardware design
Scheduling tasks in HW (possibly Software
Code 2 different HW blocks) and SW compilation
Code 3 (over different processors).
Code 4
} In real-time systems: assigning
Tasks during execution.

2011
HW SW
Hardware design Software
compilation
Compilation to a specific processor.
Currently: ASIPs

2011
Estimates before
implementation details
are known!
HW SW
compilation
High level synthesis
Component
Logic design
selection
Physical design

2011
Estimates before
implementation details
are known!
HW SW
Communication compilation
High level synthesis
Component Interface
Logic design
selection synthesis
Physical design
Simulation and verification
2011
Operating System For Embedded Application

2011
What is an Embedded OS?
• An "embedded system" is any computer system or computing

device that performs a dedicated function or is designed for use
with a specific embedded software application.
• Embedded systems may use a ROM-based operating system or

they may use a disk-based system, like a PC. But an embedded
system is not usable as a commercially viable substitute for
general purpose computers or devices.

2011
What makes a good Embedded OS?
• Modular
• Scalable
• Configurable
• Small footprint
• CPU support
• Device drivers
• etc, etc, etc...

2011
What is Real Time?
“A real time system is one in which the correctness of the

computations not only depends upon the logical
correctness of the computation but also upon the time
at which the result is produced. If the timing
constraints of the system are not met, system failure is
said to have occurred.”
- Donald Gillies
2011
What is Real Time?
“Real time in operating systems:
The ability of the operating system to provide a

required level of service in a bounded response time.”
- POSIX Standard 1003.1

2011
Hard vs. Soft Real Time
• Hard
– guaranteed worst-case response times
– absolutely, positively, first time every time
• Soft
– Kinda, sorta, usually

2011
What makes a good RTOS?
• Multi-threaded and pre-emptible

• Thread priority has to exist because no deadline driven
OS exists
• Must support predictable thread synchronization
mechanisms
• A system of priority inheritance must exist

2011
Embedded Operating System
• Task Management
– create, delete, suspend, resume
• Time Management
– system clock, generate delay
• Inter Task Communication and Synchronization
– Multitasking
• No-OS disable interrupts / enable interrupts
• With-OS enter/exit critical section

2011
Embedded Operating System (cont’)
• Inter Task Communication and Synchronization

– Wait for event, interrupt
– Exchange data, queues, shared memory
• Memory Management
– temporary data buffers
– allocate, free (critical in ES)

2011
Real Time Operating System
• Embedded applications can and will respond to

external events before deadline
• Soft real-time requirements:
– Breaking the time limit is unwanted, but is not immediately
critical
• Hard real-time requirements
– Breaking the limit is always seen as a fundamental failure

2011
Real Time Operating System Characteristics
• Bounded Interrupt Servicing

• Priority Based Scheduling
• Pre-Emptive Tasks
• Scalability

2011
Classification of Scheduling Algorithms
All scheduling algorithms
static scheduling dynamic scheduling

(or offline, or clock driven) (or online, or priority driven)
static-priority dynamic-priority
scheduling scheduling

2011
Scheduling Methodologies
– Rate Monotonic algorithm by Liu & Layland

• static priorities based on periods
• higher priorities to shorter periods
• optimal among all static priority schemes
– Earliest-deadline First
• dynamic priority assignment
• closer a task’s deadline, higher is it priority
• applicable to both periodic and aperiodic tasks
• need to calculate priorities when new tasks arrives
• more expensive in terms of run-time overheads

2011
2011
Embedded Mobile Applications

2011
Hardware / Software Components

2011
Key Technologies
• Hardware technology
– Application processors: System-on-chip (SoC) technology
– Multimedia co-processors
– Wireless co-processors
– Storage technology
– Flash memory
– HDD for handheld devices
• Software technology
– Operating systems optimized for handheld devices
– Flash file system
– Power management
– Communication support software
– Protocol stacks for wireless communications
– Communication support layer for seamless switching among different communication
methods
– Multimedia support & Optimized video/audio codec support
– 3D platforms

2011
Device Configurations

2011
Windows Mobile Applications

2011
Mobile OS: History - 1996 to now!
1996: Handheld PC (Pegasus)
– Windows CE 1.0
– Cut down version of Windows 95
– 0.5 million units sold
– Monochrome
1997: Handheld PC (Mercury)

– Windows CE 2.0
– VGA (Colour) 2000: Pocket PC 2000 (Rapier)
– MS Office Apps – Handheld PC (Galileo)
– Windows CE 3.0
– First Pocket PC (Palm-Sized PC)
2001: Pocket PC 2002 (Merlin) • Compaq iPAQ (HTC)
– Windows CE 3.0 – Simplified Windows UI
– New Shell
– Windows Media Player
2002: Pocket PC 2002 Phone Edition
– O2 XDA
2002: Smartphone 2002 (Stinger)

– Orange SPV (HTC Canary)
2003: Windows Mobile 2003 (Ozone)
– Windows CE 4.x
– Re-branded to Windows Mobile 2003
– Connectivity
• WiFi
• Bluetooth
2004: Windows Mobile 2003 Second Edition
– .NET Compact Framework
– Windows Media Player 9

2011
May 2005: Windows Mobile 5.0
The best mobile enterprise platform for integration with Office, Exchange
andNew Security
for line & Device application
of business Improved Integration with
development. Faster Application
Management Options Microsoft Office System Development
•Security improvements make
it easier to protect corporate
data • Tighter integration between • Enabling Partner Differentiation
•Additional provisioning and Microsoft Office Outlook on the • Better support for mobile line-
support functionality makes it desktop and Windows Mobile of-business application
easier to deploy and update devices increases mobile workforce development.
Windows Mobile devices. productivity
• New Office Mobile for Pocket PC
provides immediate access to Office
attachments while mobile

2011
Motorola Q – early 2006 launch
• Windows Mobile 5.0 software for Smartphone

• Part of the RAZR product line
• Landscape mode screen in QVGA
Radio: GSM / GPRS, Bluetooth, IRDA
Camera – 1.3mpix + flash
QVGA Screen (2.4’’)
QWERTY keyboard
Stereo speakers
80cc total volume
117mm x 64mm x 11.5 mm
115g with battery
Battery: 200hrs standby /
4 hrs talk

2011
HTC Wizard – September 2005
• Next version of the HTC Magician (iMate JAM)

• Windows Mobile 5.0 software for Pocket PC Phone
Radio: WiFi, Bluetooth (1.2), GSM (tri) / GPRS, IRDA

Mem: 128MB ROM, 64MB RAM
1.3mpix camera + flash
QVGA Screen (2.8’’)
Side slide QWERTY keyboard
Stereo speakers
108mm x 58mm x 18.1mm

2011
Other Devices
HTC Galaxy HTC Tornado Samsung i300 Mio A701

(GPS) (US phone) (3GB HD) (GPS)
And many more to come…
2011
Summary
• Embedded systems are everywhere

• Key challenge: optimization of design metrics
– Design metrics compete with one another
• A unified view of hardware and software is necessary to
improve productivity
• Three key technologies
– Processor: general-purpose, application-specific, single-purpose
– IC: Full-custom, semi-custom, PLD
– Design: Compilation/synthesis, libraries/IP, test/verification

2011
2011

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Computer For Future Devices Final ST Thomas July 7 2011

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Computer for Future Devices:

Embedded Computer Systems

Dr. Amlan Chakrabarti

• Embedded systems overview

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 2

• Computing systems are everywhere

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 3

• Embedded computing systems

– Hard to define. Nearly any computing and even here...

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 4

And the list goes on and on

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 6

CCD preprocessor Pixel coprocessor D2A

JPEG codec Microcontroller Multiplier/Accum

DMA controller Display ctrl

Memory controller ISA bus interface UART LCD ctrl

• Single-functioned -- always a digital camera

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 7

• Obvious design goal:

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 8

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 9

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 10

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 11

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 12

General-purpose Application-specific Single-purpose

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 13

• “Pentium” the most well-known, but total = 0

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 14

• Digital circuit designed to execute exactly Controller Datapath

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 15

• Programmable processor optimized for a Controller Datapath

particular class of applications having Control Registers

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 16

• The manner in which a digital (gate-level)

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 17

• Three types of IC technologies

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 18

• All layers are optimized for an embedded system’s

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 19

• Lower layers are fully or partially built

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 20

• All layers already exist

• The manner in which we convert our concept of

System System Hw/Sw/ Model simulat./

Test/Verification: Ensures correct

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 22

• In the past: Sequential program code (e.g., C, VHDL)

– Hardware and software Compilers

synthesis enables a unified (1950's, 1960's) Logic equations / FSM's

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 23

Flexibility Power efficiency

PLD Semi-custom Full-custom

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 24

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 26

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 27

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 28

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 29

• PowerPC (IBM, Motorola)

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 30

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 31

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 32

acakcs@caluniv.ac.in St Thomas’ College of Engineering and Technology, 7 th July, 34

• Stores large number of bits