VLSI Design Automation & FPGA Architecture - CSI - Jan - 17

CSI Workshop, Jan 17th , 2009
VLSI Design Automation &

FPGA Architecture
Amlan Chakrabarti
A.K.Choudhury School of Information Technology

University of Calcutta
Basics of VLSI Design

Introduction To VLSI Design
• VLSI Design Flow
– Several Layers of Abstraction
– No Ambiguity
Well Structured Algo: Image
Proc.
May not be always structured:
System Specification Lift Controller
Functional
Blocks that will
be implemented Architectural Design
in VLSI Not only Basic gates may be larger blocks
FF’s,2-1 MUX,DECODER etc.
Logic Design
Transistors
Circuit Design
Devices are standardized by the labs: not
Device Design much design options
Layout
Mask Generation
Fabrication
Key Issues of VLSI Design

• Concept
– Novel Idea or Product Development
• Algorithm Design
– Behavior Analysis
– Algorithm Optimization and Transformations
• Architecture Design
– Optimization of Minimum resources
– Design of Hardware components
– Prototyping on a re-configurable Hardware
• Logic design/Functional synthesis
– Design of Hardware components
– Trade off among Area /Delay/Power.
– Further improvements from logic level to circuit level.
• Physical Design
– Target to a Foundry Process
– Layout
– RC Model of Transistors
Design Metrics
• Functionality
• Cost (Non-recurring and Recurring)
• Reliability (Noise margin/immunity)
• Performance (Speed, power, energy)
• Speed (delay, operating frequency)
• Time-to-market
Challenges in Advanced Digital Design
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk
• High-Level Abstractions
• Reliability,Manufacturability
• Reuse & IP: Portability
• Power Dissipation
• Predictability
• Clock distribution
• etc.
Everything Looks a Little Different! …and There’s a Lot of Them!
Design Optimizations
• Architectural Optimizations
– An algorithm comes from an expert so we will not do the optimization of the algorithm but optimize the
architecture.
– To find the sum of numbers up to N:

• S= 1+2+3+…..+N
– Algorithm
Input N
S 0
For i = 1 to N
S S+i
Output S
• How many different storage Registers ?

• Number of Storage: N, S & I
N i S
• After the storage we have to design the datapath, i.e. we have to trace the
arithmetic and logical operation.
• The only arithmetic operation is addition.
N Counter
i S
Control Flow
N Counter
i S
Comparator
Freeze
•Whether the structure is optimized?
-We may need to replace the adder with a faster adder
•What about area and power?
-Whether all the blocks are essential or we can remove some of them,
whether all of them is 100% utilised?
• We have to see whether each of the blocks is busy in N clock

cycles
– i is changing in each clock
– Adder is working
– S is updated
– N and Comparator is not utilized all the time
• Can we start from N
– i.e. for i=N downto 1

Loadable Counter
i S
Freeze
•Eliminated one register and one comparator.

•1 NOR and one loadable up counter
•Optimization at the architectural level
• Logic Optimizations
– Let us take the example of a 2:1 Multiplexer
A A
Y
B
B
S S
Whether this is an optimized logic design?
• Number of transistor required
• NOT-2, AND 6X2,OR-6
• 20 transistors
B
S
•Number of transistor required

•NAND 4X3, NOT-2
•14 transistors
•Reduced by 6 transistors
Other Optimization Issues
• SPEED
• AREA
• POWER
In present day technology SPEED is much of more concern
than that of the AREA.
The choice between SPEED and POWER depends on the
application concerned.
Speed
Combinational
Circuit
Combinational
Circuit
Combinational
Circuit
Design 1: # of Circuit Levels-2
Combinational
Circuit Combinational
Combinational
Circuit
Circuit
Design 2: # of Circuit Levels-3

Speed Power Trade Off

•Dynamic Power is proportional to the frequency of switching
Combinational
Circuit
Which circuit
is better and
Combinational why?
Circuit
Design 1
Combinational
Circuit Combinational
Circuit
Design 2: For one half of the inputs the output is

not switched
Reduction of Critical Path in

Architectural Design
• What is a time critical path?
– The circuit path having the highest amount of delay
The R input cannot

R be changed before
7ns
Delay
of 7 ns. Combinational
Circuit
R
Stage 1 2ns. •Output in every 3ns.

•The speedup would
R
have been 3 times if
we could have split
Clock: 3ns Stage 2 3ns. into 3 equal blocks
•Can we reduce the
R
delay more?
Stage 1 2ns.
Pipelined Architecture
Data 0,3,6 1,4,7 2,5,8

in
R R R
Stage 1 Stage 1 Stage 1
R R R
Stage 2 Stage 2 Stage 2
R R R
Stage 1 Stage 1
Stage 1
R R
R Data
out
Parallel Pipelined Architecture
VLSI Design Automation
Introduction To EDA Tools

EDA Tools
• Great Design Challenges, powerful PCs…, extremely low time to market, mixed
technologies, what’s the solution?
– Need of a Savior
– Electronic Design Automation (EDA) is the answer
• What EDA offers?
– An Integrated Platform for Deisgning, Validation and Verification
– Saves Manpower and Time
– Verification through Simulation
– Validation through imposing of constraints
– Seamless Migration through each design layers

EDA vs. Manual Design

• Manual layout vs. EDA is like:
– Manual transmission vs. automatic transmission
– HTML programming vs. Frontpage
– Assembly code programming vs. compiled high-level language
• Manual layout for small, optimized designs will always be superior
• EDA techniques for larger-scale designs will always be superior

(verification, reusability, NRE, etc.)
• Goal: do careful, manual design of smaller components (cells) and

use EDA to combine them for large-scale design
EDA Tools
1. High Level Synthesis (HDLs)
2. Logic Synthesis
3. Circuit Optimization
a. transistor sizing for min delays
b. process variations
c. statistical design
4. Layout
a. floorplanning
b. place & route
c. module generation
d. automatic cell placement and routing
5. Layout Extraction
6. Simulation (SPICE for circuit-level simulation)
7. Layout - Schematic Verification
8. Design Rule Check
What EDA Tools Can Do

• “My” Design Flow
process
info, cell
Abstract Generation abstracts
Circuit Sim
Digital cell library Cadence AbGen
Cadence IC-Tools
design
Cadence IC-Tools Characterization char. info
Cadence SignalStorm
Design Standard Cell Library

Specification
Behavioral VHDL Synthesis
Design Place-and-Route
Synopsys Design
Mentor HDL Designer Analyzer Cadence First
VHDL Verilog
Encounter
Behavioral Simulation Cell Timing Simulation Interconnect Timing

Mentor ModelSim Simulation
Mentor ModelSim
Mentor ModelSim
FPGA
Field Programmable Gate Array

• Interconnection Switch:
– Based on Switch Matrix
• Configurable Logic Block (CLB):

– Based on Look Up Table (LUT)
Digilent FPGA Board

Modern FPGAs
• Flexible architectures for logic as well as application specific
processor design
• Dedicated Memory on chip
• Hardware Multipliers
• MULT_AND gates for DSP specific functions
• Hard Processor Cores (PowerPC) : Virtex-4

Conclusion
• VLSI Design is a challenging field involving various
issues
– Optimization is the key
• EDA is the Savior

– We must adapt it
• Programmable FPGA architectures gives us a platform

for VLSI Circuit Implementation
– Re-configurability is the key
acakcs@caluniv.ac.in

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CSI Workshop, Jan 17th , 2009

VLSI Design Automation &

A.K.Choudhury School of Information Technology

Basics of VLSI Design

Key Issues of VLSI Design

• Cost (Non-recurring and Recurring)

• Reliability (Noise margin/immunity)

• Performance (Speed, power, energy)

• Speed (delay, operating frequency)

Challenges in Advanced Digital Design

“Microscopic Problems” “Macroscopic Issues”

• Ultra-high speed design • Time-to-Market

• Interconnect • Millions of Gates

– To find the sum of numbers up to N:

• How many different storage Registers ?

• Number of Storage: N, S & I

• We have to see whether each of the blocks is busy in N clock

– i is changing in each clock

– N and Comparator is not utilized all the time

• Can we start from N

– i.e. for i=N downto 1

•Eliminated one register and one comparator.

•Number of transistor required

Other Optimization Issues

Design 2: # of Circuit Levels-3

Speed Power Trade Off

Design 2: For one half of the inputs the output is

Reduction of Critical Path in

The R input cannot

Stage 1 2ns. •Output in every 3ns.

Data 0,3,6 1,4,7 2,5,8

Stage 1 Stage 1 Stage 1

Stage 2 Stage 2 Stage 2

VLSI Design Automation

Introduction To EDA Tools

– Electronic Design Automation (EDA) is the answer

• What EDA offers?

– An Integrated Platform for Deisgning, Validation and Verification

– Saves Manpower and Time

– Verification through Simulation

– Validation through imposing of constraints

– Seamless Migration through each design layers

EDA vs. Manual Design

• Manual layout for small, optimized designs will always be superior

• EDA techniques for larger-scale designs will always be superior

• Goal: do careful, manual design of smaller components (cells) and

What EDA Tools Can Do

Design Standard Cell Library

Behavioral Simulation Cell Timing Simulation Interconnect Timing

Field Programmable Gate Array

• Configurable Logic Block (CLB):

Digilent FPGA Board

• Dedicated Memory on chip

• MULT_AND gates for DSP specific functions

• Hard Processor Cores (PowerPC) : Virtex-4

• EDA is the Savior

• Programmable FPGA architectures gives us a platform

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