Laser Logic State Imaging

Baohua Niu, Grace Mei Ee Khoo, Yuan-Chuan Steven Chen

Fernando Chapman, Dan Bockelman, Tom Tong
Intel Corporation
Hillsboro, OR, USA
 Purpose

Share with you:

– Introduction of the physics of Logic State
Imaging (LSI) and Laser LSI (LLSI)
– Implementation and application of LLSI
– Experimental data demonstrate
advantages of LLSI over LSI

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 Presentation Outline
• Introduction to LSI and LLSI:
– Introduction to LSI: Off state leakage “luminescence” and its
limitations
– Introduction to LLSI: Continuous wave laser signal imaging and
probing and its advantages
– Tool block diagram and procedures for LLSI vs LSI
• LLSI experiment data:
– Resolution and Signal to Noise Improvement
– Seeing those “non” emitting devices in their correct “Logic States”
• Summary and future directions:

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 IREM LSI – Off State Luminescence

Vcc Vcc
1 0 1 1 0 1
OFF ON

1 0 0 1 1 1 0 1 0 1

ON OFF

1 1 1 1 0 1
Vss Vss

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CW-SIP: Imaging Fixed Frequency Active Circuits

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 Experiment Setup-Tool Block Diagram

1
2 LLSI-Image

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4
5

6 9

8
7
Lasers LSM-Image
11
10

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 Introduce Modulation onto Vcc
0.1 0.1
VmodV
mod

Vccfub
Vccfub1

+
1
Vccfub0
Vccfub0

Vccfub2
Vcclfub2

Vccfub3
Vccfub3
0.9 Vcc
0.9 Vcc
22nm/14nm Devices
MPU/SOC Devices

‘Modulated’
Function Power
Generator Supply
Oscillo-
scope
Hi-Current DUT
Power Loadboard
Supply Tester

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Experiment Setup-Procedures

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 LLSI: Combine LSI with CW-SIP
PMOS
PMOS Mod

INV2 INV1
ON NMOS

Mod NMOS

0 1

OFF OFF ON
1 0
0

ON OFF

INV2 INV1
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LSI vs LLSI Case Studies

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Currently in Production MPU LSI vs LLSI
Currently in Production MPU LSI vs LLSI
Currently in Production SOC LLSI-No LSI from IREM

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Previous Generation SOC LLSI-No LSI from IREM
Currently in Production MPU LLSI, no LSI

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Currently in Production MPU LLSI-1319nm CW Laser

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Currently in Production MPU LLSI-1064nm CW Laser

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 Summary
• Innovative DFX features utilized to enable LLSI:
• FIVR and ODDI/ODDD
• External modulation of interested power rails/power
planes
• LLSI Advantages:
• Scalable to low Vcc (<=500mV) and ultra low leakage
(sub nA) devices and technologies.
• >50% spatial resolution
• Several fold of increase in SnR, and n/p MOSFET show
up equally
• Can see “passive” not only active “logic state” devices
• Enable easier CAD layout alignment TPT
improvement
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Future Improvements:
• Make LLSI universal, not depend on DFX and external
power rails/power planes modulation
• Further Improvement in Sensitivity of LLSI, as Off-state
leakage based LSI was sensitive to small voltage (Vd changes
~10 to 20mV [1]
• Take advantages of the CW-SIP to gain not only “static”
logic information, but also dynamic logic state information
as well as critical timing information

1) “Testing and Diagnostics of CMOS Circuits Using Light Emission from Off-State Leakage Current” Franco
Stellari et al., IEEE Transactions on Electron Devices Vol. 51, No. 9, September 2004, pg 2392.

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Acknowledgement
Intel-TMG, LTD design group:
Fabrice Paillet, Loc Mai and Gerhard Schrom
Intel TMG labs:
Zhiyong Ma, Travis Eiles, Rajiv Giridharagopal, Mitch Sacks, Tony Peterson.
Intel TMG Labs FATD team at Intel Penang:
Choon Yan Teh, Him Eng Yeoh and Seong Leong Lim
Intel TMG-PTD LYA labs:
Aamir Zia and Rajesh Duggirala, Martin von Haartman
Intel PEG/MDO JF debug labs:
Pat Pardy and his team for their support on data collected in the JF-Debug lab .
Intel TMG-Fab32:
Shane Pollard
and many others…

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