Optimizing Power @ Design Time

Circuits

Progettazione Low Power. A.A. 2020-2021

 Chapter Outline

 Optimization framework for energy-delay trade-off

 Dynamic power optimization
– Multiple supply voltages
– Transistor sizing
– Technology mapping
 Static power optimization
– Multiple thresholds
– Transistor stacking

Progettazione Low Power. A.A: 2020-2021 4

 Energy/Power Optimization Strategy

 For given function and activity, an optimal operation

point can be derived in the energy-performance space
 Time of optimization depends upon activity profile
 Different optimizations apply to active and static power
Optimization can be done here if:

- Independent of activity
- or activity is know a priori Fixed Variable No Activity
Activity Activity - Standby

Active
Design time Run time Sleep
Static

Progettazione Low Power. A.A: 2020-2021 4

 Chapter Outline

 Optimization framework for energy-delay trade-off

 Dynamic power optimization
– Multiple supply voltages
– Transistor sizing
– Technology mapping
 Static power optimization
– Multiple thresholds
– Transistor stacking

Progettazione Low Power. A.A: 2020-2021 4

 Energy-Delay Optimization and Trade-off

Energy/op Trade-off space

Unoptimized
design
Optimum curve!
Emax

Emin
Dmin Dmax Delay
Maximize throughput for given energy or
Minimize energy for given throughput
Other important metrics: Area, Reliability, Reusability
Progettazione Low Power. A.A: 2020-2021 4
 The Design Abstraction Stack
A very rich set of design parameters to consider!
It helps to consider options in relation to their
abstraction layer

System/Application Choice of algorithm

Amount of concurrency
Software
Parallel versus pipelined, general
purpose versus application specific,
(Micro-)Architecture instruction set
logic family, standard cell
Logic/RT
This Lesson

versus custom

Circuit sizing, supply, thresholds

Bulk versus SOI

Device
Progettazione Low Power. A.A: 2020-2021 4
 Some Optimization Observations

How much change in energy and delay

do we have by tuning one of the design
variables? ∂E / ∂A
SA=
∂D / ∂A A=A0
Energy

(A0,B0)
SA Sensitivities are
intrinsically negative.
f (A,B0)
SB A larger S (module) has a
higher potential for energy
f (A0,B) reduction.

D0 Delay
Energy-Delay Sensitivities
Progettazione Low Power. A.A: 2020-2021 4
 Finding the Optimal Energy-Delay Curve

Pareto-optimal:
Improving on one metric by necessity means hurting another

Energy
f (A1,B)
(A1,B0) ∆E = SA∙(∆D) + SB∙∆D

(A0,B0)
E0
∆E f (A,B0)

∆D (A1,B1)
f (A0,B)

D0 Delay
On the optimal curve (∆E =0), all sensitivities must be equal
Progettazione Low Power. A.A: 2020-2021 4
 Reducing Active Energy @ Design Time

Eactive ~   C L  Vswing  VDD

Pactive ~   C L  Vswing  VDD  f

 Reducing voltages
– Lowering the supply voltage (VDD) at the expense of clock speed
– Lowering the logic swing (Vswing)
 Reducing transistor sizes (CL) Interesting trade-off (both
– Slows down logic affect power and
 Reducing activity (a) performance)
– Reducing switching activity through transformations
– Reducing glitching by balancing logic

Progettazione Low Power. A.A: 2020-2021 4

 Circuit Optimization Framework
minimize Energy (VDD, VTH, W)
subject to Delay (VDD, VTH, W) ≤ Dcon

topology A
Constraints

Energy/op
VDDmin < VDD < VDDmax
VTHmin < VTH < VTHmax
Wmin < W topology B
 Optimization is performed w.r.t. a
Delay
well established reference case:
– Dmin sizing @ VDDmax, VTHref

We need to formulate models of energy and delay.

Progettazione Low Power. A.A: 2020-2021 4.

 Optimization Framework: Generic Network

VDD,i VDD,i+1

i i+1

Ci gCi Cw Ci+1

Gate in stage i loaded by fanout (stage i+1): fan out= Ci+1/Ci

Dynamic energy dissipated in the i-th stage  gCi + Cw + Ci+1

g is the ratio between the intrinsic output
capacitance and the input capacitance of the
gate (depends on the gate sizing)
Progettazione Low Power. A.A: 2020-2021 4.
 Dynamic Energy
2 2
Edyn  (Ci  Cw  Ci 1 ) VDD ,i  Ci (  f i)  VDD ,i
Ci  K e Si f i  (Cw  Ci 1 ) / Ci  Si1 / S i

Input and intrinsic output capacitance are prop. to sizing S

VDD,i VDD,i+1

i i+1

Ci gCi Cw Ci+1

2 2
Ei  K e S i (VDD ,i 1  VDD ,i )
= energy consumed by logic gate i
Progettazione Low Power. A.A: 2020-2021 4.
 Alpha-power based Delay Model
K dVDD C i Cw  Ci 1 1 Ci1
t p d
( )   nom (1   )
(VDD  Von ) Ci  Ci
intrinsic delay
Fit parameters: Von, d, Kd, g
4 60
simulation simulation
3.5
model 50 model
FO4 delay (norm.)

3
Von = 0.37 V tnom = 6 ps

Delay (ps)
40
2.5
ad = 1.53 g = 1.35
2 30

1.5
20
1 tp

10
0.5
(90nm technology)
0 0
0.5 0.6 0.7 0.8 0.9 1 0 2 4 6 8 10
ref
VDD / VDD Fanout (Ci+1/Ci)
VDDref = 1.2V, technology 90 nm
Progettazione Low Power. A.A: 2020-2021 4.
 Example: Inverter Chain

 Properties of inverter chain

– Single path topology
– Energy increases geometrically from input to output

1
CL
S1 = 1 S2 S3 … SN

 Goal
– Find optimal sizing S = [S1, S2, …, SN], supply voltage, and
buffering strategy to achieve the best energy-delay tradeoff

Progettazione Low Power. A.A: 2020-2021 4.

 Chapter Outline

 Optimization framework for energy-delay trade-off

 Dynamic power optimization
– Multiple supply voltages
– Transistor sizing
– Technology mapping
 Static power optimization
– Multiple thresholds
– Transistor stacking

Progettazione Low Power. A.A: 2020-2021 4.

 Multiple Supply Voltages

 Block-level supply assignment

– Higher throughput/lower latency functions are
implemented in higher VDD
– Slower functions are implemented with lower VDD
– This leads to so-called “voltage islands” with separate
supply grids
– Level conversion performed at block boundaries

 Multiple supplies inside a block

– Non-critical paths moved to lower supply voltage
– Level conversion within the block
– Physical design challenging

Progettazione Low Power. A.A: 2020-2021 4.

 Distributing Multiple Supply Voltages
Conventional Shared N-well
Gates at different Vdd Gates at different Vdd
placed in different wells placed in the same well

VDDH VDDH
VDDL VDDL

i1 o1 i1 o1
i2 o2 i2 o2

VSS VSS

VDDH circuit VDDL circuit VDDH circuit VDDL circuit

Progettazione Low Power. A.A: 2020-2021 4.
 Conventional
Better!
VDDL Row
N-well isolation
VDDH VDDL VDDH Row
VDDL Row

VDDH Row
(a) Dedicated row
VSS

VDDH VDDL
VDDH circuit VDDL circuit Region Region

(b) Dedicated region

Progettazione Low Power. A.A: 2020-2021 4.
 Shared N-Well
N-wells can be abutted but low-
Vdd PMOSs experience reverse VDDL circuit
body biasing
Shared N-well VDDH circuit

VDDH

VDDL

VSS

VDDH circuit VDDL circuit

(a) Floor plan image
Progettazione Low Power. A.A: 2020-2021 4.
 Lessons: Multiple Supply Voltages

 Two supply voltages per block are

optimal

 Optimal ratio between the supply

voltages is 0.7

Progettazione Low Power. A.A: 2020-2021 4.