Four-Bit Serial Adder

By Huong Ho, Long Nguyen, Lin-Kai Yang

Ins: Dr. David Parent Date: May 17th, 2004

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Agenda
Abstract Introduction Project Details Summary of Results Conclusions

Abstract
We designed an 4-bit serial adder that operated at 200 MHz and used of power 10.75mW and occupied an area of 192x60 um.

Introduction
Bit-serial structure is designed to process the input one bit at a time, generally using the results of the operations on the first bit to influence the processing of subsequent bits. Because it passes all the bits through the same logic, bitserial reduces a significant amount of required hardware. Typically, the bit-serial approach requires 1/nth of the hardware required for the equivalent n-bit parallel design. Bit-serial structure reduces signal routing (1-bit signals instead of n-bit signals) and higher-speed operation (one adder and a register rather than an n-bit adder).
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Introduction (cont.)
The price of this logic reduction is that the serial hardware takes n clock cycles to execute, while the equivalent parallel structure executes in one clock cycle. Bit-serial architectures have been used successfully in many applications that are dealing with a bit stream such as signal processing, audio, video etc. It was extremely popular in the 2-5u technology range.

4-bit Serial Adder Schematic

Longest Path Calculations

Logic Level 1 Gates DFF pav 0.625 Cg to drive #CDNs #CDPs #LNs LPs Wn Wp Cg

2
3 4 5 6 7 8

INV
AOI 1 AOI 2 NAND2 NAND2 INV DFF

0.625
0.625 0.625 0.625 0.625 0.625 0.625

30
7 2*12 21 7 7 2*7

1
10 7 3 3 1

1
10 7 2 2 1

1
3 2 2 2 1

1
3 2 1 1 1

1.5
2.57 3.45 1.5 1.5 1.5

2.5
4.32 5.80 2.5 2.5 2.5

7
12 21 7 7 7

5ns PHL .625ns 8

Note: All widths are in microns and capacitances in fF

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D-Flip Flop Calculations

Parts NOR2 slave Driver mux slave NOR2 master Keeper mux master Driver mux master Cg to drive 14 12.1 13.1 NA 11.4 Wn 1.56 1.5 1.65 1.5 1.5 1.65 Wp 5.50 1.5 3.0 5.16 1.5 2.85 Cg of gate 12.1 5.1 8.0 11.4 5.1 7.6 #CDs #SPMOS #SNMOS 3 NA 5 3 NA 5 2 NA 2 2 NA 2 1 NA 2 1 NA 2

Keeper mux slave NA

PHL

PHL
2

.313ns
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D-Flip Flop Schematic

D-Flip Flop Waveform

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Full Adder Schematic

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Full Adder Waveform

PHL 562 ps

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4-bit Serial Adder Schematic

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4-bit Serial Adder Waveform

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4-bit Serial Adder Layout

Area = 192 x 60 um

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Power Consumption

P = 10.75 mW
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DRC & Extraction

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4-Bit Serial Adder LVS

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Summary of Results
Parameters Speed Power (4-bit) Specification 200 MHz None Simulation Results 200 MHz 10.75mW= 93.3W/cm 192 x 60 um

Area (4-bit)

Minimum

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Acknowledgements
Thank you Dr. Parent for being so patient!!! Thanks to Cadence Design Systems for the VLSI lab. Thanks to our classmates who helped us in the lab.

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