LPC2148

Agenda
• Features
• PLL
• GPIO
• Timer/Counter
• DAC
• ADC
Features
• The LPC2141/42/44/46/48 microcontrollers, introduced by NXP
semiconductors, are based on a 16-bit/32-bit ARM7 TDMI-S CPU with
real-time emulation and embedded trace support.
• They have an embedded high-speed flash memory ranging from 32 kB
to 512 kB and a 128-bit wide memory interface.
• They also have 8 kB of on-chip RAM, one or two 10-bit ADCs, a 10-bit
DAC, two 32-bit timers/counters, a watchdog timer, a PWM unit,
aReal-Time Clock (RTC) with independent power and 32 kHz clock
input, multiple UART, I2C, and SPI buses, and a PLL and an on-chip
oscillator for clocks.
LPC2148 PLL
• There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The
PLL0 is used to generate the CCLK clock (system clock) while the PLL1 has
to supply the clock for the USB clock at the fixed rate of 48 MHz.
• The PLL0 and PLL1 accept an input clock frequency in the range of 10
MHz to 25 MHz only. This frequency is multiplied up to the range of 10
MHz to 60 MHz for the system clock and 48 MHz for the USB module
using a Current Controlled Oscillators (CCO). The USB module needs a
48MHz clock, which is generated by a PLL circuit.
• PLL unit uses a CCO, which operates in the range of 156 MHz to 320
MHz. The clock for the PLL module is generated by dividing the CCO
frequency by 2, 4, 8, or 16.
PLL block diagram
Registers for PLL
• PLLCON (PLL Control Register)
• PLLCFG (PLL Configuration Register)
• PLLSTAT (PLL Status Register)
• PLLFEED
PLLCON (PLL Control Register)
• The PLLCON register contains the bits that enable and connect the PLL.
• Enabling the PLL allows it decide the current multiplier and divider values,
while connecting the PLL causes the processor and all chip functions to run
from the PLL output clock.
PLLCFG (PLL Configuration Register)
• The PLLCFG register contains the PLL multiplier and divider values.
Values written to this register do not take effect until a valid PLL feed
sequence has taken place.
PLLSTAT (PLL Status Register)
• Reading this register provides the actual values controlling the PLL, as
well as the status of the PLL.
PLLFEED (PLL Feed Register)
• A correct feed sequence must be written to the PLLFEED register in
order for changes to the PLLCON and PLLCFG registers to take effect.
The feed sequence is:
• Write the value 0xAA to PLLFEED.
• Write the value 0x55 to PLLFEED.

• The two writes must be in the correct sequence, and must be

consecutive APB bus cycles. If either of the feed values is incorrect, or
this condition is not met, any changes to the PLLCON or PLLCFG
register will not become effective.
PLL frequency calculation
• = frequency from the crystal oscillator(XTAL)/external clock
• = frequency of the PLL Current Controlled Oscillator(CCO)
• CCLK = PLL output frequency (CPU Clock)
• M = PLL Multiplier value from the MSEL bits in the PLLCFG register
• P = PLL Divider value from the PSEL bits in the PLLCFG register
• PCLK = Peripheral Clock which is derived from CCLK

• The PLL output clock is

CCLK = M x
or
CCLK = / (2 x P)
• Conversely, the CCO output clock is given by:

= CCLK x 2 x P
or
= x M x 2 x P

The divider value D must be chosen such that is within its defined
frequency limits.
Step 1: PLL setup
• Choose an oscillator frequency (FOSC). CCLK must be the whole (non-
fractional) multiple of FOSC.
• M = CCLK / FOSC (between 1 and 32)
• The value written to the MSEL bits in PLLCFG is M − 1.
• The value of D written to the PSEL bits in PLLCFG is 00 for P = 1; 01 for
P = 2; 10 for P = 4; 11 for P = 8
• Since CCLK = 60 MHz, we can calculate the value of P using the
formula:
P = / (2 X CCLK)

• We know that the range of is 156 MHz to 320 MHz.

• Substituting = 156 MHz, we get
P = 156 MHz / (2 X 60 MHz) = 1.3
• Substituting = 320 MHz, we get
P = 320 MHz / (2 X 60 MHz) = 2.67
• Since the value of P must be an integer, the integer between 1.3 and
2.6 is 2, so the PSEL bits should be ‘01’
• Now, the multiplier is calculated using the formula
M = CCLK / .

• The PLL0CON and PLL0CFG registers should be configured.

PLL0CON=0x01; // PPLE=1 & PPLC=0 to enable PLL

PLL0CFG=0x24;
/* set the multipler to 5 (actually 4) i.e., 12
x 5 = 60 Mhz (M - 1 = 4). For P=2, set PSEL bits
to 01 in PLL0CFG. */
Step 2: Apply the feed sequence
• Feed Sequence is nothing but assignment of 2 particular ‘fixed’ values
to a register related to the PLL block. This register is called ‘PLL0FEED’.
And those fixed values are 0xAA and 0x55 are in order.
• Hence, the sequence would be:

PLL0FEED=0XAA;
PLL0FEED=0X55;
Step 3: Connect the PLL
• Check whether PLL has locked on to the desired freq by reading the
lock bit in PLL0STST register. If it locked then connect the PLL by
setting the 2nd bit in PLL0CON Register.

while((PLL0STAT&(1<<10))==0);
/* Wait till PLL has locked on to the desired freq.
by reading the lock bit in the PPL0STAT register */
PLL0CON=0x03; //Enable & Connect PLL

• Applying the feed sequence again completes the PLL setup.

Code
// This program is for 60Mhz clk & 60Mhz pclk
void set_pll(void)
{
PLL0CON=0x01; // PPLE=1 & PPLC=0 to enable PLL
PLL0CFG=0x24; // Set M to 5 (actually 4) and P=2
PLL0FEED=0XAA; // Feed
PLL0FEED=0X55;
while((PLL0STAT&(1<<10))==0);
// Wait till PLL has locked on to desired frequency
PLL0CON = 0x03;// Enable & Connect PLL
PLL0FEED = 0XAA; // Feed
PLL0FEED = 0X55;
VPBDIV = 0x01; // PCLK is same as CCLK i.e., 60Mhz
}
GPIO
LPC2141/2/4/6/8 has 2 32-bit General Purpose I/O ports, PORT0 and
PORT1. There are 3 registers which are used to control the functions of
the GPIO pins:

• PINSEL0 – Controls functions of Port0.0 – Port0.15

• PINSEL1 – Controls functions of Port0.16-Port0.31
• PINSEL2 – Controls functions of Port1.16-Port1.31
• PORT0 and PORT1 are controlled via two groups of 4 registers:
IOPIN
• The register will give the logic value of the pin regardless of whether
the pin is configured for input or output, or an alternate function.
IOSET
• This register is used to produce a HIGH level output at the port pins
configured as OUTPUT mode by writing 1. If any pin is configured as
an input or a secondary function, writing 1 to the corresponding bit in
the IOSET has no effect.
IODIR
• This word accessible register is used to control the direction of the
pins when they are configured as GPIO port pins. The direction bit for
any pin must be set according to the pin functionality.
IOCLR
• This register is used to produce a LOW-level output at port pins
configured as GPIO in an OUTPUT mode by writing 1 to the pin.
Example code
#include<lpc214x.h>
void delay()
{
unsigned int i;
for(i=0;i<30000;i++);
}
void main()
{
IO0DIR |= 0XfffffFFF; // Port 0 is now the output pin
while(1) {
IOSET0 |=0XfffffFFF; //All pins are high (LED is ON)
delay();
IOCLR0 |=0XFFFfffff; //All the pins are low(LED is OFF)
delay();
}
}
Timer/Counter
Features:
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Up to four 32-bit capture channels per timer
• Four 32-bit match registers that allow:
• Continuous operation with optional interrupt generation on match.
• Stop timer on match with optional interrupt generation.
• Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers
Timer Working Operation
• The tick rate of the Timer Counter (TC) is controlled by the 32-bit
number written in the Prescaler Register (PR).
• There is a Prescale Counter (PC) which increments on each tick of the
PCLK.
• When it reaches the value specified in the prescaler register, the timer
count is incremented and the Prescaler Counter (PC) is reset.
Registers Used in LPC2148 Timer
Register Description
Interrupt Register: The IR can be read to identify which of 6(4-match, 2-Capture)
IR possible interrupt sources are pending. Writing Logic-1 will clear the corresponding
interrupt.
Timer Control Register: The TCR is used to control the Timer Counter
TCR functions(enable/disable/reset).
Timer Counter: The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is
TC controlled through the TCR.
PR Prescaler Register: This is used to specify the Prescaler value for incrementing the TC.
Prescale Counter: The 32-bit PC is a counter which is incremented to the value
PC stored in PR. When the value in PR is reached, the TC is incremented.
Count Control Register: The CTCR selects between Timer and Counter mode, and in
CTCR Counter mode selects the signal and edge(s) for counting.
Registers in LPC2148 Timer (cntd)
Register Description
Match Registers: The Match register values are continuously compared to the
Timer Counter value. When the two values are equal, actions can be triggered
MR0-MR3 automatically. The action possibilities are to generate an interrupt, reset the
Timer Counter, or stop the timer. Actions are controlled by the settings in the
MCR register.
Match Control Register: The MCR is used to control the resetting of TC and
MCR generating of interrupt whenever a Match occurs.
Capture Registers: TC value is loaded to this Capture Register when there is an
CR0 - CR4 event on the CAPn.0 - CAPn.4
Capture Control Register: The CCR controls which edges of the capture inputs
CCR are used to load the Capture Registers and whether or not an interrupt is
generated when a capture takes place.
Interrupt Register (IR)

• Interrupt Register consists of flag bits for Match Interrupts and

Capture Interrupts.
• In the IR register, Bit 0 is for MR0 interrupt, Bit 1 is for MR1 interrupt,
etc. Bits 4 to 7 are for Capture Register Interrupts Bit 4 for CR0
interrupt, Bit 5 for CR1 interrupts, etc.
• If an interrupt is triggered, then the corresponding bit in the IR
register is set to 1. Manually writing a logic 1 on the bit of the IR
register will reset the interrupt.
Timer Control Register (TCR)
• It is used to enable/disable or reset the Timer Counter.
• When the first bit (TSR [0]) is 0, Timer Counter and Prescale Counter are disabled.
When the first bit is 1, the counters are enabled.
• When the second bit (TSR [1]) is 1, both the counters (Timer Counter and Prescale
Counter) are reset on the next positive edge of the peripheral clock and remain
reset until the second bit is set to 0.
Count Control Register (CTCR)
Count Control Register is used to set either Timer mode or Counter
Mode. If Counter Mode is selected, the counter pin and the edges
(rising, falling, or both) can be selected using CTCR.

Timer Counter Register (TC)

The value in the Timer Counter register in incremented when the value
PC reaches its terminal value as set by the PR register. If the PC is reset
before reaching its maximum value, then the TC will count to the
maximum possible value and resets. This event does not cause an
interrupt, but a Match register can be used to detect an overflow if
needed.
Prescale Register (PR)
Prescale Register specifies the maximum value for the Prescale Counter.
When the Prescale Counter (PC) is equal to PR, the TC is incremented
on the next clock and PC is cleared.

Prescale Counter Register (PC)

Prescale Counter increments on every peripheral clock to the value
stored in the PR. When the value in the PC is equal to the value in the
PR, the PC is reset and TC is incremented by 1 on the next clock cycle.
Hence, PC defines the resolution of the Timer.
Match Control Register (MCR)
• The Match Control Register is used to control the actions to be
performed when the value in the Match Register (MR) matches with
the value in the Timer Counter (TC).
• Bits 0 to 2 in MCR (i.e. MCR [0], MCR [1] and MCR [2]) are used for
MR0 register, bits 3 to 5 for MR1, bits 6 to 8 for MR2, and bits 9 to 11
for MR3 respectively.

Match Registers (MR0 – MR3)

The Match register values are continuously compared to the Timer
Counter value. When the two values are equal, actions can be triggered
automatically, controlled by MCR.
Capture Control Registers (CCR)
The Capture Control Register is used to control whether one of the four
Capture Registers is loaded with the value in the Timer Counter when
the capture event occurs and whether an interrupt is generated by the
capture event.

Capture Registers (CR0 -CR3)

Each Capture register is associated with a device pin and may be loaded
with the Timer Counter value when a specified event occurs on that
pin. The settings in the Capture Control Register determine whether the
capture function is enabled and whether a capture event happens on
the rising edge of the associated pin, the falling edge, or on both edges.
Configuring the timer
This is the sequence for Setting up Timers:
i. Set appropriate value in TxCTCR
ii. Define the Prescale value in TxPR
iii. Set Value(s) in Match Register(s) if required
iv. Set appropriate value in TxMCR if using Match registers / Interrupts
v. Reset Timer – Which resets PR and TC
vi. Set TxTCR to 0x01 to Enable the Timer when required
vii. Reset TxTCR to 0x00 to Disable the Timer when required
Prescaler Register Value Calculation
The delay or time required for 1 clock cycle at ‘X’ MHz is given by :
Delay = 1/(X*1000000) Seconds

Hence, in our case, when PR=0 i.e. TC increments at every PCLK the delay required for
TC to increment by 1 is:
Delay = (0+1)/(60*1000000) Seconds

Similarly, when we set PR = 59999 the delay will be:

Delay = (599999+1)/(60*1000000) Seconds
Delay = 1ms

Hence, the delay required for TC to increment by 1 will be 1ms.

Code
void delay(unsigned int z)
{
T0CTCR=0x0; //Select Timer Mode
T0TCR=0x00; //Timer off
T0PR=59999; //Prescaler value for 1ms
T0TCR=0x01; //Timer ON
while(T0TC<z); // Wait till timer reaches z ms
T0TCR=0x00; //Timer OFF.
}
LPC2148 DAC
DAC Control Register – DACR
As per the datasheet, it is implemented as a string DAC, which is the simplest
form of DAC consisting of 2N resistors in series, where N = no. of bits, which
simply forms a Kelvin-Varley Divider. LPC214x DAC has only 1 output pin,
referred to as AOUT. The Analog voltage at the output of this pin is given as:
VAOUT = VALUE * VREF / 1024

Pins related to LPC2148 DAC block:

Pin Description
AOUT (P0.25) Analog Output pin. Provides the converted Analog signal which is referenced to
VSSA i.e. the Analog GND. Set Bits[19:18] in PINSEL1 register to [10] to enable this
function.
VREF This is the voltage reference pin used by DAC for conversion.
VDDA, VSSA VDDA is Analog Power pin and VSSA is Ground pin used to power the DAC module.
These are generally same as VCC and GND but with additional filtering to reduce
noise.
DAC Programming procedure
i. First, configure P0.25/AOUT pin as DAC output using PINSEL
Register.
ii. Then set settling time using BIAS bit in DACR Register.
iii. Now write 10-bit value (which we want to convert into analog
form) in VALUE field of DACR Register.
Code
int main(void)
{
initTimer0();
PINSEL1 |= (1<<19); //Select AOUT function for P0.25.
unsigned int value=1; //Binary value for Conversion

while(1) {
if(value > 1023) value=0; //For 10-bit DAC,
// max-value is 2^10 - 1 = 1023
DACR = (value<<6);
delayMS(10); value++;
}
}
LPC2148 ADC
Features:
• LPC2148 has two inbuilt 10-bit Successive Approximation ADC. ADC0 has
six channels (AD0.1-AD0.6). ADC1 has 8-Channels (AD1.0-AD1.7).
• ADCs in LPC2148 use Successive Approximation technique to convert
analog signal into digital form.
• Their operating frequency is 4.5 MHz (max.), which decides the conversion
time.
• The ADC reference voltage is measured across GND to VREF
• 10 bit conversion time ≥2.44 µs.
• Burst conversion mode for single or multiple inputs.
• Input multiplexing among 6 or 8 pins (ADC0 and ADC1).
Registers Used For ADC
Register Description
ADxCR A/D Control Register: Used for Configuring the ADC

ADxGDR A/D Global Data Register: This register contains the ADC’s DONE bit and the
result of the most recent A/D conversion

ADxINTEN A/D Interrupt Enable Register: To enable/disable interrupts

ADxDR0 - A/D Channel Data Register: Contains the recent ADC value for respective
ADxDR7 channel
A/D Status Register: Contains DONE & OVERRUN flag for all the ADC
ADxSTAT channels

ADxGSR A/D Global Start Register: This address can be written (in the AD0 address
range) to start conversions in both A/D converters simultaneously.
Configuring the ADC
Below are the steps for configuring the LPC1768 ADC.
i. Configure the GPIO pin for the ADC function using the PINSEL register.
ii. Enable the CLock to ADC module.
iii. Power on the internal ADC module by setting ADCR.PDN bit (ADCR’s 21st bit).
iv. Select the Particular channel for A/D conversion by setting the corresponding
bits in ADCR.SEL (bit 0 – bit 7).
v. Set the ADCR.START bit for starting the A/D conversion for the selected channel
(ADCR’s 24th bit).
vi. Wait for the conversion to complete, ADGDR. The DONE bit will be set once the
conversion is over.
vii. Read the 10-bit A/D value from ADGdR.RESULT.
Code
int val;
PINSEL1 = 0x01000000; /* P0.28 as AD0.1 */
AD0CR=0x00200802; //CLKDIV=4, ADC ON, Channel 1 selected
AD0CR |= (1<<24); //Start conversion
while((AD0GDR & (1<<31)) == 0);
val = AD0GDR;
// Similarly for AD1
References and further reading
• https://embetronicx.com/arm7-lpc2148-tutorials/
• http://www.ocfreaks.com/cat/embedded/lpc2148-tutorials/
https://www.electronicwings.com/arm7