STM32

Microcontroller architecture
• A typical microcontroller includes a processor, memory and
Input/Output (I/O) peripherals on a single chip. Its components may
be extended to include: Digital I/O, Analog I/O, Timers,
Communication interfaces, Watchdog, etc.
STM32 hardware setup
• Power supply
It is required to power on your device to make it start working.
• Oscillators
The STM32 embeds an internal RC oscillator, and a more accurate and stable
external crystal.
• Debugger
After programming the MCU, the code is analyzed using a debugger, which
comes along with the IDE. The debugger is connected to the device in one of
the two ways:
• SWD (Serial Wire Debug), which uses 2 pins: it is designed for micro debugging
• JTAG (Joint Test Action Group) with 5 or 4 pins: it is designed for checking faults
in boards in production.
System peripherals
• GPIO
• EXTI
• NVIC
• DAC
• ADC
GPIO
• The function of a GPIO pin is customizable and can be controlled by
the software.
• Pin Mode : Each port bit of the general-purpose I/O (GPIO) ports can
be individually configured by software in several modes:
• Input : no pull-up and no pull-down or pull-up or pull-down
• Output : push-pull or open-drain with pull-up or pull-down capability
• Alternate function : to connect the IO port to an internal peripheral digital
line. Supports push-pull or open-drain with pull-up or pull-down capability.
• Analog: to connect the IO port to an internal peripheral analog line. The pull-
up and pull-down resistors are disabled (by hardware) in analog mode.
Pin configurations
Setting the pin characteristics
• No pull-up and no pull-down or pull-up or pull-down in the
GPIOx_PUPDR register, needs to be selected to be coherent with the
hardware schematics.
• Push-pull or open-drain in the GPIOx_OTYPER register, needs to be
selected to be coherent with the hardware schematics.
• Output speed in the GPIOx_OSPEEDR register needs to be tuned to
achieve the expected level of performance (rising and falling times)
GPIO circuit diagram
• Every IO port implements the logic shown in the image below:
Output-speed configuration
• Change the rising and falling edge when the pin state changes from
high to low or low to high.
• For example, low speed is optimal for toggling GPIO at 1 Hz, while
using SPI at 45 MHz requires very high speed setting.
Example code
// ...
while
{
HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin);
// For example, GPIOD pin 13
HAL_Delay(500);
}
EXTI
• The EXTI peripheral is used to get an interrupt when a GPIO is
toggling. It can also wake up the system when a wake up event
occurs, before propagating an interrupt to the client processor.
• Up to 16 GPIO pins can be configured as external interrupts. One EXTI
can be selected for each index.
• Each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising,
falling, or both).

• EXTI<index> = GPIO<one_bank><index>
 STM32L1xx external interrupt/event controller
• External devices can interrupt CPU via GPIO pins
(Some microcontrollers have dedicated interrupt pins)
• Up to 16 external interrupts (EXTI0-EXTI15), plus 7 internal events

PR IMR RTSR FTSR

IRQ
to
NVIC
External
interrupt
signal
(GPIO pin)

15
19
Nested Vectored Interrupt Controller
(NVIC)
 NVIC manages and prioritizes external interrupts in
Cortex-M
45 IRQ sources from STM32L1xx peripherals
 NVIC interrupts CPU with IRQ# of highest-priority IRQ signal
 CPU uses IRQ# to access the vector table & get intr. handler start
address

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 Interrupt signal: from device to CPU Peripheral Device
(“Enabled” in three places) Registers:
In each peripheral device: Enable Flag
 Each potential interrupt source has a separate
xIE xF
enable
 Set tobit
enable the peripheral to send an interrupt signal to
the CPU
 Clear to prevent the peripheral from interrupting the CPU &
 Each potential
 Flag interrupt
set by hardware source
when has a separate
an “event” occurs flag bit IRQn
 Interrupt request = (flag & enable)
 Test flag in software if interrupt not desired
 ISR software must clear the flag to acknowledge the
request
Nested Vectored Interrupt Controller (NVIC)
NVIC
 Receives all interrupt requests
 Each has an enable bit and a priority within the NVIC n
 # of highest-priority enabled interrupt sent to the CPU PRIMASK
Within the CPU:
 Global interrupt enable bit in PRIMASK register &
CPU
 Interrupt if priority of IRQ < that of current thread
10
 Access interrupt vector table with IRQ# Interrupt
NVIC setup: enable interrupts
Each IRQ has its own enable bit within the
NVIC
NVIC only considers IRQs whose enable bits are
set
Interrupt Set Enable Register: each bit
enables one interrupt
 CMSIS function: NVIC_EnableIRQ(n); //set
bit n to enable IRQn
Interrupt Clear Enable Register: each bit
Examples: EXTI0_IRQn = //External interrupt EXTI0 is IRQ
disables
6; one interrupt
TIM3_IRQn #6 = 29 ; //Timer TIM3
 CMSIS function: NVIC_DisableIRQ(n); //set bit n
interrupt is IRQ #29
to disable IRQn
Usage:
NVIC_EnableIRQ(EXTI0_IRQn); //enable external
For convenience,
interrupt EXTI0stm32l1xx.h defines
NVIC_DisableIRQ(TIM3_IRQn); //disable
 NVIC: interrupt pending flags
 Each IRQ has an interrupt pending flag within the NVIC
Pending flag set by NVIC when it detects IRQn request, and
IRQn status changed to “pending”
IRQn status changes to “active” when its interrupt handler is
entered
NVIC clears pending flag when handler exited, changing status
to “inactive”

 If IRQn still active when exiting handler, or IRQn reactivates while

executing the handler, the pending flag remains set and triggers
another interrupt Avoid duplicate service by clearing IRQn
pendingstatus
Pending flag in software:
can be checked:
CMSIS
 CMSIS function:
function: NVIC_ClearPendingIRQ(IRQn);
NVIC_GetPendingIRQ(IRQn);
Software can force IRQn into pending state to simulate an IRQn

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request
 CMSIS function: NVIC_SetPendingIRQ(IRQn);
 NVIC: interrupt
priorities
Each IRQn assigned a priority within the NVIC
NVIC selects highest-priority pending IRQ to send to
CPU
 Lower priority# = higher priority (default value = 0)
 Higher priority interrupt can interrupt lower priority one
 Lower priority interrupt not sent to CPU until higher priority
interrupt service completed
 If equal priorities, lower IRQ# selected
Priorities stored in NVIC Interrupt Priority Registers
 STM32L1xx uses 4-bit priority value (0..15)
(NVIC registers allocate 8 bits per IRQ#, but vendors may use fewer
bits)
Set priority via CMSIS function:

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NVIC_SetPriority(IRQn, priority);
Ex: NVIC_SetPriority(EXTI0_IRQn, 1); //set ext. intr.
Cortex-M Interrupt Process
1. Interrupt signal detected by CPU
2. Suspend main program execution
 finish current instruction
 save CPU state (push registers onto stack) Pre-IRQ
 set LR to 0xFFFFFFF9 (indicates interrupt top of stack
return)
 set IPSR to interrupt number
 load PC with ISR address from vector table
3. Execute interrupt service routine
 save other registers to be used 1
(ISR)
clear the “flag” that requested the interrupt IRQ
top of stack
 perform the requested service
 communicate with other routines via global
variables
 restore any registers saved by the ISR 1
4. Return to and resume main program by executing
BX LR
 saved state is restored from the stack, including PC
4 1 C compiler takes care of saving/restoring registers
DAC
• A digital to analog converter is a system that converts a digital input
signal or a value into an analog signal. It takes in a digital number or
value as an input and converts it into an analog voltage. The voltage
level corresponds to the binary number in the DAC output register.
• It supports 8 or 12 bit mode
Example code
uint16_t dac_value=0;

// The following code runs in a loop

HAL_DAC_Start(&hdac1, DAC_CHANNEL_2);
HAL_DAC_SetValue(&hdac1,DAC_CHANNEL_2,DAC_ALIGN_12B_R,dac_value);
if (dac_value < 4095)
dac_value++;
else
dac_value=0;
HAL_Delay(1);

Inside the if conditional statement, we check if dac_value is lower than 4095 (0xFFF) which is
the maximum output value for a 12-bit resolution DAC:
If the value is lower than the maximum value, it is incremented. If not, it is reset back to zero.
Then, we add a 1ms delay in order to have a stable output value.
ADC
• The analog-to-digital converters allows the microcontroller to accept
an analog value like a sensor output and convert the signal into the
digital domain.
Features

Functions for conversions:

HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
DMA
• DMA stands for Direct Memory Access controller.
• DMA is a bus master and system peripheral providing high-speed data
transfers between peripherals and memory, as well as memory-to-
memory.
• Data can be quickly moved by DMA without any CPU action, keeping
CPU resources free for other operations.
• A DMA controller has 7 channels. Each channel is dedicated to
managing memory access requests from one or more peripherals.
DMA transfer flow
i. At the beginning of the main program, HAL_DMA_Init() is called to
reset all peripherals, initialize flash interface and systick.
ii. HAL_DMA_Start() starts the DMA transfer after the configuration of
source and destination addresses, as well as the length of data to
be transferred.
iii. HAL_DMA_PollForTransfer() polls for the end of current transfer. In
this case a fixed timeout can be configured by user depending on
his application.
iv. Once the transfer is completed, it is recommended to handle the
return values to make sure the program worked as expected.
Example code
uint8_t Buffer_Src[] = {0,1,2,3,4,5,6,7,8,9};
uint8_t Buffer_Dest[10];
HAL_DMA_Start(&hdma_memtomem_dma1_channel1,
(uint32_t) (Buffer_Src), (uint32_t)
(Buffer_Dest), 10);
// Polling
while(HAL_DMA_PollForTransfer(
&hdma_memtomem_dma1_channel1,
HAL_DMA_FULL_TRANSFER, 100) != HAL_OK)
{
__NOP();
}
DMA interrupt mode flow
i. DMA intialization is generated in main.c.
ii. HAL_DMA_Start_IT: Start DMA buffer transfer
iii. DMA1_Channel1_IRQHandler is generated in stm32f4xx_it.c: it
indicates whether the DMA process is half/complete or an error was
detected.
iv. HAL_DMA_IRQHandler is defined in stm32f4xx_hal_dma.c: Process
interrupt information.
v. DMA_XferCpltCallback: Data correctly transferred complete callback
function.
vi. DMA_XferErrorCallback: Error was detected Error callback function.
 Example code
void XferCpltCallback(DMA_HandleTypeDef *hdma)
{
__NOP(); //Line reached only if transfer was successful.
// Toggle a breakpoint here
}

// In main():
uint8_t Buffer_Src[]={0,1,2,3,4,5,6,7,8,9};
uint8_t Buffer_Dest[10];
hdma_memtomem_dma1_Channel1.XferCpltCallback=&XferCpltCallback;
HAL_DMA_Start_IT(&hdma_memtomem_dma1_Channel1,
(uint32_t)Buffer_Src,(uint32_t)Buffer_Dest,10);
References and further reading
• https://wiki.st.com/stm32mcu/wiki/Category:Getting_started_with_S
TM32_system_peripherals
• https://wiki.st.com/stm32mpu/wiki/Category:Peripherals_-_Hardwar
e_blocks