BIPOLAR JUNCTION

TRANSISTOR
 BIPOLAR JUNCTION TRANSISTOR

• Transistor => solid state device, whose operation depends

upon the flow of the electric charge carriers with in the solid.
• Current controlled device
• Three terminal device (emitter, base and collector )with two
junctions- emitter- base junction and collector base junction
• Like two PN junctions connected back to back
• Advantages
 compact size, light weight, rugged construction, more
resistive to shocks and vibrations, instantaneous
operation, low operating voltage, high operating
efficiency, long life
 CONSTRUCTION
• Consists of Si or Ge crystal
( commonly used is Si) in
which a layer of N type
material is sandwiched
between two layers of P
type material (NPN
transistor) or a layer of P
type material is sandwiched
between two layers of N
type material (PNP
transistor)
 TRANSISTOR TERMINALS
 EMITTER
 COLLECTOR
 BASE
 TRANSISTOR TERMINALS
EMITTER
• To supply the majority charge carriers(electrons in case
of NPN transistor and holes in the case of PNP
transistor ) to base
• The emitter will be always forward based w.r.t. base so
that it will be able to supply majority charge carriers to
base
• Heavily doped so that it will be able to inject a large
number of charge carriers
• Moderate size in order to maintain heavy doping
without mesh formation in it
COLLECTOR
• Its main function is to collect the majority charge
carriers
• It is always reverse biased so as to remove the charge
carriers away from the junction
• Moderately doped to avoid the chances of mesh
formation even after taking the carriers from the
emitter
• Large in size to withstand the temperature generated
at the collector
BASE
• Middle section of the transistor
• It is lightly doped to reduce the recombination within
the base so as to increase the collector current
• Very thin in comparison to either emitter or collector
so that it may pass most of the injected charges to the
collector
• The forward biased emitter- base junction offers the
low resistance to the emitter current where as the
collector base junction offers the high resistance to the
collector current.
• As the resistance of the emitter- base junction is very
small as compared to the collector base junction, the
forward biased applied to the emitter- base junction is
very small whereas the reverse bias applied to the
collector base junction is much large
OPERATING REGIONS OF BJT
• CUTOFF REGION
• ACTIVE REGION
• SATURATION REGION
TRANSITOR CIRCUIT CONFIGURATIONS
COMMON BASE CONFIGURATION
 INPUT CHARACTERISTICS
 For given value of VCB, the curve
is just like that of a forward biased
PN junction because emitter base
junction in forward bias mode is
similar to a PN junction
 With the increase in VCB , it
conducts better. This is because
large collector base voltages cause
depletion layer at the collector
base junction to penetrate deeper
 Cutin/offset/ thershold voltage
 Emitter current increases rapidly
with small increase in VEB =low
dynamic input resistance
 OUTPUT CHARACTERISTICS
 The collector current Ic varies with
VCB only for a very low voltge but
transistor never operated in the
region
 In active region, Ic is almost equal
to IE and appears to remain
constant when VCB is increased.
 Although the Ic is practically
independent of VCB, however if VCB
is increased beyond a certain value
Ic increases rapidly => punch
through or reach through
 Output resistance is very high
 In cutoff region , a small collector
current flows => collector leakage
current ICBO or ICO
 In satuartion region, Ic flows even
when VCB =0.
 CB configuration is rarely used in audio frequency
circuits because its current gain is less than unity and
its input and output resistances are quite different
COMMON EMITTER CONFIGURATION
 INPUT CHARACTERISTICS

 The input characteristics is

similar to that of a forward
biased diode because the base
emitter region of the transistor
is a diode and it is forward
biased
 Here the current increases less
rapidly with increase in base
emitter voltage VBE= input
resistance is larger in CE
configuration.
 OUTPUT CHARACTERISTICS
 The collector current Ic varies
with VCE for VCE between 0 and
1 V and then becomes almost
constant and independent of
VCE

 The output resistance of CE

configuration is less than that of
CB configuration
COMMON COLLECTOR CONFIGURATION
INPUT CHARACTERISTICS OUTPUT CHARACTERISTICS
 COMPARISON OF DIFFERENT
TRANSISTOR CONFIGURATION
 TRANSISTOR BIASING
 The process of applying DC voltages across the different
terminals of a transistor is called biasing.
 For faithful amplification, it is essential that the
(i) Emitter base junction is forward biased
(ii) Collector base junction is reversed biased
(iii) Proper zero signal collector current
 For achieving the faithful amplification, fulfilment of the following
basic conditions is essential
1. Proper Zero signal Collector current
2.Minimum Proper Base emitter Voltage at any instant
3. Minimum Proper Collector Emitter Voltage at any instant
• The condition 1 and 2 ensure the emitter base junction remains
properly forward biased and the condition 3 ensures that the
collector base junction remains properly reverse biased
• The proper flow of the zero signal collector current and the
maintenance of proper collector emitter voltages during the
passage of signal is called transistor biasing
• The circuit used for transistor biasing is called biasing circuit
 TRANSITOR LOAD LINES
 Load line is defined as the locus of operating point on the
output characteristics of the transistor.
 It is the line on which the operating points move when AC
signal is applied.
 DC LOAD LINE
 Let Vcc is the supply voltage to the
collector,
Rc is the collector resistance ,
VCE is the collector to emitter voltage
 Applying Kirchoff’s second law


 This equation is plotted in the
output characteristics of the
transistor with VCE and Ic as
variables
 , where m is
the slope of the line and c is the
intercept of the line on vertical
current axis
 Considering the following two particular situations
 (i) when VCE=0, = > saturation point A
 (ii) when Ic=0, = > cutoff point B
 By joining these two points, DC load line is obtained
 The DC load line represents the dynamic
characteristics of the device
 The DC load line gives the values of the Ic and VCE
corresponding to zero signal conditions.
 QUIESCENT POINT
 It is the point on the DC load line
which represents DC collector
emitter voltage and collector
current in absence of AC signal.
 Also called as operating point
 Because the variations in VCE and
Ic takes place about this point
when the signal is applied,
 The best position for this point is
the midway between the cutoff
and saturation point where the
 AC LOAD LINE

 When the AC signal is applied, the

transistor voltage VCE and collector
current Ic vary above and below the Q
point. The Q point is common to both
DC and AC load line.
 The AC load line gives the values of
VCE and Ic when AC is applied.
 AC load line is steeper than DC load
line but the two lines intercept at Q
1. In CE configuration, collector supply voltage
Vcc=10V, load resistance Rc is 8kΩ.Draw DC
load line. Determine the operating point Q for
zero signal if base current is 15µA and β is 40.
 SELECTION OF OPERATING POINT
• For faithful amplification
proper selection of operating
point or quiescent point is
important.
• The transistor operates linearly
with it is made to operate in the
active region
• Depending up on the position of
Q point, the input signal is
faithfully amplified and
reproduced at the output
terminal.If the Q point is not
suitably selected, it will result
in unfaithful amplification
(clipping of positive or negative
• The device can be made to operate at ant where in the
operating region
• The operating region is the area of current and voltages within
the maximum limits for the particular devise. The maximum
rating are maximum collector current Ic max, maximum
collector voltage VCE max, maximum collector power
dissipation Pc max.
 BIAS STABILIZATION
• The maintenance of the operating point stable is
known as stabilization
 FACTOR AFFECTING THE STABILITY
OF Q POINT
1. Temperature dependence of Collector current

Ic=β IB+(1+β)ICO

– Reverse saturation current ICO

– Transistor gain β
– Base emitter voltage
2.Individual variations
– The values of β and VBE are not exactly same for any two transistors even of same
type.so if the transistor is replaced by another one, the Q point shifts
3. Thermal runaway
– Ic increases with increases of temperature.Being a cumulative process, it can lead to
increase in temperature of device resulting in the burn out of transistor
MEANS FOR ACHIEVING STABILITY FOR
OPERATING POINT
 Stabilization technique
 Compensation technique
 STABILITY FACTOR
 It is the degree of success achieved in stabilization of Ic
even when the Ico is varied
 It is defined as the rate of change of collector current w.r.t.
Ico keeping β and V constant
BE
 Stability factor Sv is defined as the rate of change of
collector current w.r.t. VBE keeping β and Ico constant

 Stability factor Sβ is defined as the rate of change of

collector current w.r.t. β keeping VBE and Ico constant
 GENERAL EXPRESSION FOR
STABILITY FACTOR S
 In active region,
GENERAL EXPRESSION FOR STABILITY
FACTOR Sβ
 In active region,
TRANSISTOR BIASING CIRCUITS
 Establish the operating point in the middle of the
active region of characteristics
 Stabilize the Ic against the temperature variation
 Make operating point independent of the transistor
parameters
SIMPLE BIASING CIRCUIT
FIXED BIAS CIRUIT
 By applying Kirchoff’s second law for branch circuit
starting from VBB to ground

 For linear amplifier

STABILITY FACTOR
VOLTAGE DIVIDER BIAS OR SELF
BIAS
Precise Circuit Analysis
STABILITY FACTOR, S
STABILITY FACTOR, S β
STABILITY FACTOR, Sv
1. For the voltage divider bias configuration of fig
shown determine (i) Ic, (ii) Vcc, (iii) V , (iv) V ,
E CE

(v) V and (vi) R , given the Vc = 10.6 V

B 1
2. Determine the values of R1 and R2 for the given
circuit. Given that Vcc = 24V, Rc =330Ω ,R =
E

130Ω , V =0.3V, Ic =20mA,α =0.99 and stability

BE

factor S=10.
3. A Ge transistor with β= 49 has a self biasing
arrangement. Given Vcc = 10 V, RL=1Ω,VCE=5V,
Ic=4.9A as VBE= 0.2V. The stability factor is
derived to be 10. Obtain the values of R 1, R2, RE .
4. A voltage divider bias circuit has the following
datas
I =1mA, VCEQ=5V, β=100, S=8, RE=1kΩ,
CQ

RL=1kΩ .Obtain the value of R1 and R2.

COLLECTOR TO BASE BIAS OR
BASE BIAS WITH COLLECTOR
FEEDBACK
 Circuit analysis
STABILITY FACTOR,S
STABILITY FACTOR,SV BE
For the given network ,determine Ic, VCE,VB and VC

V = 20V, R = 4.7kΩ, RB=680kΩ, C1=10µF and

CC C

C2 =10µF.
Ans.
VCC = (IC+IB)RC +IBRB+ V BE
= (1+β) IBRC + IBRB + V BE
IB = = 15.5µ A
IC =1.86mA
VCE= VCC -(IC+IB)RC = 11.19V
VC= VCE = 11.19V
• Determine the resistor RB for a fixed bias and
collector to base bias and compare the stability
factors.
VCC=12V,RL=33KΩ, IB=0.3mA, β=100, VCE=6V.
 BIAS COMPENSATION
 Reduces the amplification signal
 Compensation techniques
DIODE COMPENSATION FOR VARIATIONS
IN BASE EMITER VOLTAGE V
BE
DIODE COMPENSATION FOR
VARIATIONS IN Ico
THERMISTOR COMPENSATION
• Minimise change in Ic due to variation of
VBE,B,Ico with temperature
 HYBRID PARAMETERS
• TWO PORT NETWORK
........(1)

........(2)
h11 Short circuit input impedance parameter or input
impedance with output short circuited

h12 open circuit reverse transfer voltage ratio parameter

h short circuit forward transfer current ratio
21

parameter

h22 open circuit output admittance parameter

Sl no h parameter CE CB CC

1 h 11 h ie h ib h ic

2 h 12 h re h rb h rc

3 h 21 h fe h fb h fc

4 h22 h oe h ob h oc
HYRID PARAMETERS OR h
PARAMETERS
HYBRID EQUIVALENT CIRCUIT OF
TRANSISTOR
ANALYSIS OF TRANSISTOR USING h
PARAMETERS
 CURRENT GAIN Ai
 INPUT IMPEDANCE Zin

Slide 96
 VOLTAGE GAIN Av
 OUTPUT IMPEDANCE Zo

Slide
HYBRID EQUIVALENT CIRCUIT OF CE
CONFIGURATION
 ib and Vc are selected as independent variables
 VB= f1(ib , Vc )
 Ic= f2(ib , Vc )
 Making use of Taylor’s series expansion, about zero
operating point
=> β
CE TRANSISTOR AMPLIFIER USING h
PARAMETERS
CE AMPLIFIER AC EQUIVALENT CIRCUIT

VOLTAGE DIVIDER BIAS

CE AMPLIFIER h PARAMETER
EQUIVALENT CIRCUIT

Slide101
Slide 99
 CE AMPLIFIER AC EQUIVALENT
CIRCUIT
WITH AN UNBYPASSED EMITTER RESISTOR
CE AMPLIFIER h PARAMETER
EQUIVALENT CIRCUIT
Voltage divider bias
 INPUT IMPEDANCE Zin
Input impedance to transistor base

the actual circuit Impedance

With unbypassed emitter resistance
 INPUT IMPEDANCE Zin

Input impedance to transistor base

the actual circuit Impedance

Voltage divider bias
 OUTPUT IMPEDANCE`
The device output impedance

circuit actual impedance

 VOLTAGE GAIN Av

circuit
 CURRENT GAIN

Device current gain

Over all current gain

current gain without external load R L
Over all current gain
LIMITATIONS OF h PARAMETERS
Q1:A transistor used in CE arrangement has the
following set of h parameters when the dc operating
point is Vce=10 V and Ic=1mA.
hie=2000Ω ; hoe= mho; hre= ; hfe=50
Determine (i) input impedance (ii) current gain and
(iii) voltage gain.
The ac load seen by the transistor is RL=600Ω. What will
be the approximate values using reasonable
approximations
 ASSIGNMENT
 Explain the role of coupling capacitor and
emitter bypass capacitor