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Lec 4 MOSFET II
Lec 4 MOSFET II
Lec 4 MOSFET II
Lec 4
MOS Transistor II
kT N A N D
where 0 ln
q ni2
• Assuming NA small compared to ND and 0 small compared to V (the
reverse bias voltage which ranges from 0 to –VDD),
1
xd NA
V
1 1 1 1
xd V 2
V
S S NA S NA
• Thus, for constant voltage scaling, NA => S2NA, and ND => S2ND
• On the other hand, for full scaling, VA => V/S giving:
1 1 1 1 1 V
xd V 2
V
S S NA S NA S NA S
Oxide
LS LD
VB=0
13 CMOS Digital Integrated Circuits
Small Geometry Effects
Channel Depletion Region Charge Reduction (Cont.)
• The reduction in charge is represented by the change of the
channel depletion region cross-section from a rectangle of length
L and depth xdm to a trapezoid with lengths L and L-ΔLS- ΔLD and
depth xdm. This trapezoid is equivalent to a rectangle with length:
L S L D
L1
2L
• Thus, the channel charge per unit area is reduced by the factor:
1 L S L D
2L
• Next, need ΔLS and ΔLD in terms of the source and drain junction
depths and depletion region junction depth using more geometric
arguments. Once this is done, the resulting reduction in threshold
voltage VT due to the short channel effect can be written as:
xdm xj n+
x dD
Junction Depletion Region
(p-Si)
0.8
0.7
Threshold Voltage (V)
0.6
0.5
0.4
0 1 2 3 4 5 6
Channel Length (µm)
16 CMOS Digital Integrated Circuits
Small Geometry Effects
Narrow-Channel Effect
• W is on the same order of the maximum depletion region thickness xdm.
• The channel depletion region spreads out under the polysilicon at its
rises over the thick oxide. Thus, there is extra charge in the depletion
region.
1 x dm
• The increase in VT0Vdue
T0
to q S i Ncharge
this 2extra A 2 F is
C ox W
xdm
QNC W QNC
LM
Gate
Source tox Oxide Drain
(p+) n+ L xj n+ (p+)
Substrate (p-Si)
• LM: mask length of the gate
• L: actual channel length
• LD: gate-drain overlap
• Y: typical diffusion length
• W: length of the source and drain diffusion region
21 CMOS Digital Integrated Circuits
MOSFET Capacitances
Oxide Capacitances
• Parameters studied so far apply to steady-state (DC) behavior. We
need add parameters modeling transient behavior.
• MOSFET capacitances are distributed and complex. But, for
tractable modeling, we use lumped approximations.
• Two categories of capacitances: 1) oxide-related and 2) junction.
Inter-terminal capacitances result as follows:
Cgb D
Cgd Cdb
MOSFET
G B
(DC Model)
Cgs Csb
S
22 CMOS Digital Integrated Circuits
MOSFET Capacitances
Overlap Capacitances
• Capacitances Cgb, Cgs, and Cgd
• Have the thin oxide as their dielectric
Overlap Capacitances
• Two special components of Cgs and Cgd caused by the lateral
diffusion under the gate and thin oxide
CGS(overlap) = CoxWLD
CGD(overlap) = CoxWLD
LD: lateral diffusion length
W : the width of channel
Cox = εox/tox: capacitance per unit area
• Theses overlap capacitances are bias independent and are added
components of Cgs and Cgd.
Junction Capacitances
• Capacitances associated with the source and the drain
• Capacitances of the reversed biased substrate-to-source and
substrate-to-drain p-n junctions.
• Lumped, but if the diffusion used as a conductor of any length,
both its capacitance and resistance need to be modeled in a way
that tends more toward a distributed model which is used for
resistive interconnect.
xj
G
D
W
NAND NAND
Q j Aq xd A 2 S i q 0 V
N A ND N A ND
The capacitance found by differentiating Qj with respect to V to
give:
dQ j AC j 0
C j (V ) 1/ 2
dV (1V / 0)
with
S q NAND 1
C j0 i
2 N A N D 0
30 CMOS Digital Integrated Circuits
MOSFET Capacitances
Junction Capacitance - Approximations
Approximation for Manual Calculations
• The voltage dependence of Cj(V) makes manual calculations
difficult. An equivalent large-signal capacitance for a voltage
change from V1 to V2 can be defined as
Ceq = Q/V = (Qj(V2)-Qj(V1))/(V2-V1)
• The formula of this equivalent large-signal capacitance is derived
in the book with the final version:
Ceq =ACj0Keq
where Keq (0<Keq<1) is the voltage equivalence factor,
K eq
2 0
0 V 2 0 V 1
V 1 V 2