Multiplexer based Design

Multiplexer
I0
2:1
mux Z Z = A' I 0 + A I 1
I1

I0
I1
4:1 Z Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
I2 mux
I3

A B

I0
I1
I2
I3
I4
8:1
Z Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
mux
I5 A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
I6
I7 n
In general, Z = S 2 -1m I
k=0 k k
A B C in minterm shorthand form for a 2 n :1 Mux
 Implementing three variable expression

Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C

= A' B' (C') + A' B (C') + A B' (0) + A B (1)

1 0 A B C F
0 1 0 0 0 1 C 0
1 C F
2 F 0 0 1 0 C 1 4:1
0 3 8:1 0
0 1 0 1 2 MUX
0 4 MUX C 1
0 0 1 1 0 3
5 S1 S0
1 6 1 0 0 0
0 A B
1 7 S2 S1 S0 1 0 1 0
1 1 0 1
A B C 1 1 1 1 1
 MUX for combinational logic realization

Example: Implement function .

realized by an 8x1 MUX using the three variables A, B, and C as

the three selections, and the function values corresponding to
the eight minterms as the eight MUX inputs.

the same function can be realized by a 4x1 MUX (with additional NOT
gates) using variables A and B as the two selections. Output function f
is represented in terms of variable C

two variables B and C enter the truth table, the function is realized by a 2x1 MUX with
more extra logic
F(X,Y,Z) = ∑ m( 1,2,6,7)
F(A,B,C,D) = ∑ m( 1,3,4,11,12,13,14,15)