FET Basics

• Fundamentals: definition, structure,

operations and characteristics
• Biasing of FET
• Modeling of FET and small signal analysis
• DC and AC load line analysis
• FET amplifier configurations and design
• FET applications
 Introduction of FET
 An FET (field-effect transistor) operates on either electrons or holes flow. Hence it
is a unipolar transistor, i.e. single-type of current carriers.
 Whereas a BJT is a current controlled device, a FET is a voltage controlled device.
 It has an extremely high input resistance (in the order of 107 to 1012).
 It requires virtually no input (gate) current IG = 0 A.
 Also used as amplifier and logic switches
 It is preferred over BJT as the input stage of a multi-stage amplifier.
 FETs generate low noise and are more temperature stable than BJTs. (It does not
depend on electron-hole pair for current conduction.)
 Therefore they are more suitable for amplification of very small signals.
 As there is no minority carrier storage time (no p-n junction recovery time) for FETs,
they are widely used (very popular indeed) in switching applications.
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4
5
6
7
8
FET analogy, bias, and currents
The source of water
pressure can be likened to
the applied voltage from
drain to source that will
establish a flow of water
(electrons) from the spigot
(source). The “gate"
through an applied signal
(potential), controls the
flow of water (charge) to
the "drain” The drain
and source terminals are
at opposite ends or the n-
channel as introduced in
Figure

9
 Introduction of FET
 There are two major types of FETs.
(a) Junction FET (JFET), and
(b) Metal Oxide Semiconductor (or silicon) FET (MOSFET)
(i) Depletion-type MOSFET (D-MOSFET)
(ii) Enhancement-type MOSFET (E-MOSFET), and
(iii) Vertical MOSFET (VMOS).

 Each type can be further classified into n-channel or p-channel MOSFETs.

 Major Types of FETs

FET

JFET MOSFET

p-channel n-channel Depletion Type Enhancement Type

p-channel n-channel
Conventional VMOS
Structure

p-channel n-channel p-channel n-channel

 Metal Oxide Silicon FET (MOSFET)
 There are two basic types of MOSFET

- Depletion-type MOSFET (D-MOSFET)

- Enhancement-type MOSFET (E-MOSFET)

 The gate terminal of a MOSFET is insulated from its channel

region by the Silicon Oxide (SiO2) layer.

 MOSFET is also called an Insulated-Gate FET (IGFET).

 FET Properties
• Advantages:
– High input impedance (M)
(Linear AC amplifier system)
– Temperature stable than BJT
– Smaller than BJT
– Can be fabricated with fewer processing
– BJT is bipolar – conduction both hole and electron
– FET is unipolar – uses only one type of current carrier
– Less noise compare to BJT
– Usually use as logic switch

• Disadvantages
– Easy to damage compare to BJT

13
JFET

14
JFET Fundamentals

15
 Junction FET
• There are 2 types of JFET
– n-channel JFET
– p-channel JFET

• Three Terminal
– Drain – D
– Gate -G
– Source – S

Water analogy for the JFET

n-channel JFET p-channel JFET control mechanism
N-channel JFET
• N channel JFET:
– Major structure is n-type material (channel) between
embedded p-type material to form 2 p-n junction.
– In the normal operation of an n-channel device, the Drain
(D) is positive with respect to the Source (S). Current flows
into the Drain (D), through the channel, and out of the
Source (S)
– Because the resistance of the channel depends on the
gate-to-source voltage (VGS), the drain current (ID) is
controlled by that voltage
N-channel JFET
• Current can flow initially because plenty of electrons are
available in the channel.
• Gate : Apply negative voltage to increase the depletion
width, so as to reduce the current. When the gate
voltage is negative enough, current will stop.
• Hence, this is a depletion device.
N-channel JFET
• Pinch off in JFET (that bop)
P-channel JFET
• P channel JFET:
– Major structure is p-type material (channel) between
embedded n-type material to form 2 p-n junction.
– Current flow : from Source (S) to Drain (D)
– Holes injected to Source (S) through p-type channel
and flowed to Drain (D)
 JFET Characteristic Curve (N-Channel)
• To start, suppose VGS=0
• Then, when VDS is increased, ID increases. Therefore, ID is
proportional to VDS for small values of VDS
• For larger value of VDS, as VDS increases, the depletion layer
become wider, causing the resistance of channel increases.
• After the pinch-off voltage (Vp) is reached, the ID becomes
nearly constant (called as ID maximum, IDSS-Drain to Source
current with Gate Shorted)

ID versus VDS for VGS = 0 V.

JFET for VGS = 0 V and 0<VDS<|Vp|

Channel
becomes
narrower as
VDS is
increased
Pinch-off (VGS = 0 V, VDS = VP).
Application of a negative voltage to the
gate of a JFET.
 JFET Characteristic Curve (N-Channel)
• For negative values of VGS, the gate-to-channel
junction is reverse biased even with VDS=0
• Thus, the initial channel resistance is higher (in which
the initial slope of the curves is smaller for values of
VGS closer to the pinch-off voltage (VP)
• The resistance value is under the control of VGS
• If VGS is less than pinch-off voltage, the resistance
becomes an open-circuit ;therefore the device is in
cutoff (VGS=VGS(off) )
• The region where ID constant – The saturation/pinch-
off region
• The region where ID depends on VDS is called the
linear/triode/ohmic region
n-Channel JFET characteristics curve
n-Channel JFET characteristics curve
n-Channel JFET characteristics curve
with IDSS = 8 mA and VP = -4 V.

JFET Characteristic Curve

 JFET Characteristic Curve (P-Channel)
• Operation is almost the same as n-channel FETs.

• Voltage polarity and current direction reversed.

• BUT… for p-channel devices,

– The carriers are holes (not electrons). So, mobility is
lower and minority carrier lifetime shorter.
– Consequence: p-channel devices are usually POORER!
• Higher threshold voltage, higher resistance, and lower current capability.
p-Channel JFET
p-Channel JFET characteristics with IDSS = 6 mA
and VP = +6 V.
Characteristics for n-channel
JFET
Characteristics for p-channel
JFET

+
+

P
 Operation of n-channel JFET
• JFET is biased with two voltage sources:
– VDD
– VGG
• VDD generate voltage bias between Drain (D) and Source
(S) – VDS
• VDD causes drain current, ID flows from Drain (D) to
Source (S)
• VGG generate voltage bias between Gate (G) and Source
(S) with negative polarity source is connected to the
Gate Junction (G) – reverse-biases the gate; therefore
gate current, IG = 0.
• VGG is to produce depletion region in N channel so that it
can control the amount of drain current, ID that flows
through the channel
 Transfer Characteristics

The input-output transfer characteristic of

the JFET is not as straight forward as it is
for the BJT. In BJT:

IC= IB

which  is defined as the relationship

between IB (input current) and IC (output
current).
 Transfer Characteristics..

In JFET, the relationship between VGS (input

voltage) and ID (output current) is used to
define the transfer characteristics. It is called
as Shockley’s Equation:
2
 VGS 
ID = IDSS  1 -  VP=VGS (OFF)
 VP 
The relationship is more complicated (and not
linear)
As a result, FET’s are often referred to a
square law devices
 Transfer Characteristics…
• Defined by Shockley’s equation:
2
 V 
I D  I DSS 1  GS  VP  VGS ( off )
 VGS 
 ( off ) 

• Relationship between ID and VGS.

• Obtaining transfer characteristic curve axis point
from Shockley:
– When VGS = 0 V, ID = IDSS
– When VGS = VGS(off) or Vp, ID = 0 mA
 Transfer Characteristics

JFET Transfer Characteristic Curve JFET Characteristic Curve

 Exercise 1
Sketch the transfer defined by I DSS = 12 mA and
VGS(off) = - 6V

VGS ID  ID 
VGS = VP 1 - 
0 IDSS  IDSS 
2
0.3Vp IDSS/2  VGS 
ID = IDSS  1 - 
0.5Vp IDSS/4  VP 
Vp 0 mA
 Exercise 1
Sketch the transfer defined by I DSS = 12 mA and
VGS(off) = Vp= - 6 V
IDSS

2
 VGS 
ID = IDSS  1 - 
 VP 
VGS =0.3VP IDSS/2
 ID 
VGS =0.5VP IDSS/4 VGS = VP 1 - 
 IDSS 
Answer 1
 Exercise 2
Sketch the transfer defined by
IDSS = 4 mA and VGS(off) = 3 V

VGS ID  ID 
VGS = VP 1 - 
0 IDSS  IDSS 
2
0.3Vp IDSS/2  VGS 
ID = IDSS  1 - 
0.5Vp IDSS/4  VP 
Vp 0 mA
 Exercise 2
Sketch the transfer defined by IDSS = 4 mA and VGS(off) = 3V

IDSS 2
 VGS 
ID = IDSS  1 - 
 VP 
IDSS/2
IDSS/4 VP  ID 
VGS = VP 1 - 
 IDSS 
VGS =0.3VP
VGS =0.5VP
Answer 2
JFET Biasing

45
 DC JFET Biasing
• Just as we learned that the BJT must be biased for
proper operation, the JFET also must be biased for
operation point (ID, VGS, VDS)
• In most cases the ideal Q-point will be at the
middle of the transfer characteristic curve, which is
about half of the IDSS.
• 3 types of DC JFET biasing configurations :
– Fixed-bias
– Self-bias
– Voltage-Divider Bias
 Fixed-bias
+ VDD • Use two voltage
sources: VGG, VDD
RD
• VGG is reverse-
C2
biased at the
+ Gate – Source
C1 +
VDS (G-S) terminal,
+ VGS
_ thus no current
Vout
RG
+ _
flows through RG
Vin (IG = 0).
_ VGG

Fixed-bias
 Fixed-bias..
• DC analysis
– All capacitors replaced with open-circuit
VDD

RD

+
VDS
_
+ VGS
RG _

Loop 1
VGG
 Fixed-bias…
1. Input Loop
• By using KVL at loop 1:
VGG + VGS = 0
VGS = - VGG

– For graphical solution, use VGS = - VGG to draw the load line
– For mathematical solution, replace VGS = -VGG in Shockley’s
Eq. ,therefore:
2 2
 VGS   
ID 
 I DSS 1    I DSS 1  VGG 
 VGS ( off )   VGS ( off ) 
   
2. Output loop
- VDD + IDRD + VDS = 0
VDS = VDD – IDRD

3. Then, plot transfer characteristic curve by using Shockley’s Equation

Example : Fixed-bias

Determine the following

network:

1. VGSQ
2. IDQ
3. VD
4. VG
5. VS
2
 VGS 
ID = IDSS  1 - 
 VP 
Mathematical Solutions
VGSQ = - VGG = - 2
2 2
 VGS   -2 
I DQ = I DSS  1 -  = 10mA  1 - 
 VP   -8 
= 10mA  0.75   5.625mA
2

VDS = VDD - I D R D = 16 -  5.625mA  2k 

= 16V - 11.25V = 4.75V
 Graphical solution for the network

Draw load line for:

VGSQ = - VGG = - 2

VDS = 4.75V
VD = 4.75V
VG = - 2V
VS = 0V
 Self-bias
• Using only one voltage source
DC analysis of the self-bias configuration.

Since IG  0A, VRG  IGRG

thus VRG  0A,

Q point for VGS

 Graphical Solutions:
Defining a point on the self-bias line.

VGS ID
0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
 Graphical Solutions:
Sketching the self-bias line.

I D = I DSS 2

VGS = -I D R S
I DSS R S
=-
2
VDS = VDD - I D  R S + R D 

VS = I D R S
 Mathematical Solutions

• Replace in the Shockley’s Equation:

2
 V 
I D  I DSS 1  GS  VP  VGS ( off )
 VP 
therefore ;
2
 ( I D RS ) 
I D  I DSS 1  
 VP 
• By using, quadratic equation and formula, choose value of I D that
relevant within the range (0 to IDSS): nearly to IDSS/2

• Find VGS by using ;also choose VGS that within

the range (0 to VP)
Example : Self-bias configuration

Determine the following for the network

1. VGSQ
2. I DQ
3. VD
4. VG
5. Vs
Graphical Solutions:
Sketching the transfer characteristics curve

Vgs ID
0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
Sketching the self-bias line

When I D = 4mA, VGS = - 4V

When I D = 8mA, VGS = - 8V

Graphical Solutions: Determining the Q-point

IDQ=2.6mA
VGSQ=-2.6mV

Q-point
 Mathematical Solutions
2
 V 
I D  I DSS 1  GS  recall VGS   I D RS
 VP 
2
 (  I D RS ) 
 I DSS 1  
 VP 
2 2
 I (1k )    6  I D (1k ) 
ID  8m1  D   8 m  
  6    6 

8m
36

36  6kI D  6kI D  1MI D
2

2
36 I D  0.288  96 I D  8kI D
2
8kI D  132 I D  0.288  0
I D1  13.9mA I D2 1  2.588mA
VGS   I D RS VGS   I D RS
 13.9mA(1k )  2.588mA(1k )
 13.9V  2.6V
therefore ; choose I D  2.588mA and VGS  2.6V
Solutions
VGSQ = - 2.6V
IDQ = 2.6mA

ID=IS
VDS = VDD - I D  R D + R S 
= 20V - 2.6mA  4.3kΩ 
= 8.82V
Voltage-divider bias

IG=0A

A
Redrawn network

R2
VG = VDD
R1 + R 2
Sketching the network equation for the voltage-
divider configuration.

VGS = VG
VG - VGS - VRS = 0 I D =0mA

VGS = VG - VRS VG
ID 
VGS = VG - I D R S RS VGS =0V
Effect of RS on the resulting
Q-point.
Example : Voltage-divider bias

Determine the following for the network

1. I DQ andVGSQ
2. VD
3. VS
4. VDS
5. VDG
Solutions
R2
VG = VDD
R1 + R 2

=
 270kΩ 16V  VDD
2.1MΩ + 0.27MΩ 2
= 1.82V

VGS = VG - I D R S
= 1.82V - I D 1.5kΩ 

When I D = 0mA, VGS = + 1.82V

+1.82V
When VGS = 0V, I D = = 1.21mA
1.5kΩ
 Determining the Q-point for the network
VGS = 1.82V - I D 1.5kΩ 

VDS = VDD + VSS - I D  R S  R D 

= VDS + VS = 8.82V + 2.6V = 11.42V
IDQ=2.4mA
VGSQ=-1.8V
 Mathematical solutions
• How to get IDS, VGS and VDS for voltage-
divider bias configuration by using
mathematical solutions?
Exercise 3:

Determine the
following for the network

1. I DQ andVGSQ
2. VDS
3. VD
4. VS
 Drawing the self bias line

VGS + I D R S - 10V = 0

VGS = 10V - I D 1.5k 

When I D = 0mA, VGS = 10V

10V
When VGS = 0V, I D = = 6.67mA
1.5kΩ
Determining the Q-point
IDQ=6.9mA
VGSQ=-0.35V
VDS = VDD -  VSS  - I D  R S + R D 
= 20 + 10 - (6.9mA)(1.8kΩ + 1.5kΩ)
= 7.23V
VD = VDD - I D  R D  = 7.58V

VS = VD - VDS
= 7.58V - 7.23V = 0.35V
Exercise 4

Determine the required

values of R D and R S
Determining VGSQ for the network .

VRD VDD  VDQ 20V  12V

RD = = 
I DQ I DQ 2.5mA
= 3.2k

  VGSQ    -1
RS = =  0.4k
I DQ 2.5mA
MOSFET

78
 Enhancement and Depletion MOSFET
 Enhancement — the channel is originally not
conducting when gate voltage is 0, and we
have to apply a positive gate voltage (bigger
than a threshold Vth or VT) to make it conduct
(enhance it).

 Depletion — In fact, we also have another

kind of MOSFET, in which the channel can
conduct even when gate voltage is not
applied. Then, we need to apply reverse gate
voltage to cut it off. This is called depletion
MOSFET.

 NOTE THAT DUE TO A SEMICONDUCTOR

DOPING PROPERTY:
 For n-channel MOSFET, both enhancement and
depletion types can be made.
 For p-channel MOSFET, only enhancement type can
be made.
 E-MOSFET
 The structure of an E-MOSFET does not have a physical channel between
the source and drain terminals during transistor fabrication, as shown
below.
 It is because of this reason; the gate-source voltage must be large enough
to attract the current carriers into the region directly beneath the gate
terminal to induce a channel in the substrate.
 These carriers form a channel that is able to carry current from the drain
terminal to the source terminal.

Source Gate Drain

Terminal Terminal Terminal
Metal
SiO Contact
2

n-doped material
p-substrate Induced n-Channel

n-channel Enhancement-type MOSFET (NMOS)

 E-MOSFET (cont’d)

 E-MOSFET can only Enhancement Mode

operate in the E-MOSFET
enhancement mode.
 The operating voltages VDS VGS
for the various type of
E-MOSFET are shown
in the Table. n-channel + value +ve
(NMOS) > VT

p-channel –value –ve

(PMOS) > VT
 E-MOSFET (NMOS)
 n-channel physical structure:
Source Gate Drain
Terminal Terminal Terminal
Metal Drain Terminal (D)
SiO Contact
2
Gate Substrate
Terminal (G) Terminal
n-doped
material Induced n-channel Source Terminal (S)
p- substrate

n-channel Enhancement-type MOSFET

 Circuit symbol:

Drain Terminal (D)

Gate (G)

Source Terminal (S)

n-channel ENMOSFET
 E-MOSFET (PMOS)
 p-channel physical structure:
Source Gate Drain
Terminal Terminal Terminal
Metal
SiO2 Contact

p-doped
material Induced p-Channel
n-substrate

p-channel Enhancement-type MOSFET

 Circuit symbol:

Drain Terminal (D) Drain Terminal (D)

Gate Substrate Gate

Terminal (G) Terminal Terminal (G)

Source Terminal (S) Source Terminal (S)

p-channel ENMOSFET
 Operation of n-channel E-MOSFET (NMOS)
 E-MOSFET can only operate in the enhancement modes.
 Since there is no physical channel built into the structure, when VGS= 0 V, there
is no current ID flow between drain terminal and the source terminal.
 When VGS is biased positive at the gate terminal G for a n-channel E-MOSFET,
negative charged carriers (the free electrons) are induced into the area directly
beneath the gate terminal insulator.
 The charged carriers (the free electrons) are actually minority carriers within the
p-substrate.
 These carriers will form an n-type channel (consists of free electrons) stretching
from the drain terminal D to the source terminal S, facilitating the drain current ID
to flow through.
 The value of VGS that is just sufficient to produce a significant channel for current
to flow from drain region D to the source region S is known as the Threshold
Voltage, VT. The value of VT is typically in the range from 1 to 3V.
 E-MOSFET Operation Modes (NMOS)
 There are three operation
modes for MOSFET
 Saturation region
 Linear/Triode/Ohmic
 Cutoff
 As VDS increases, the channel
pinches down at the drain end
and iD increases more slowly.
When VDS > VGS – VT, iD
becomes constant.
 Gate current = 0 (always)
 The channel conduction is
determined by VGS
 Characteristic of enhancement-type MOSFET
(E-MOSFET operation in the saturation)
I (mA) I (mA)
D D
D ID

ID=K(VGS–VT)2 VGS = 9V G
VGS VDS
S
VGS = 8V
VGS = 7V

VGS = 6V
VGS = 5V
VGS = 4V > VT

0 V V (V) VGS = VT VDS (V)

T GS
(a) Transfer Characteristic (b) Output Characteristic (drain curves).

ENMOSFET VGS – ID characteristics

• Because of no channel between Drain to Source n-channel ENMOSFET is capable of
operating with ID=0 at VGS=0. ID will conduct starting from the point defined by (I D = 0
when VGS = VT )(VT is the transition frequency of ENMOSFET
• The saturation current is proportional to (V GS–VT)2: ID = K. (VGS–VT)2
 Output characteristic of E-MOSFET
 E-MOSFET can only operate I
D
(mA)
in the enhancement modes.
 Hence, the gate-source VGS = 9V
voltage VGS must be larger
than the threshold voltage VT. VGS = 8V
 No current (ID = 0A) flows VGS = 7V
through the E-MOSFET when
VGS = 6V
the gate-source voltage VGS is
VGS = 5V
smaller the threshold voltage
VGS = 4V > VT
VT.
VGS = VT VDS (V)

(b) Output Characteristic (drain curves).

E-MOSFET in Triode Region

88
 Transfer characteristic of E-MOSFET (VGS – ID)

 The transfer characteristic curve obeys the

following equation.
I (mA) ID = K (VGS - VT)2 for (VGS > VT).
D

 The values of the threshold voltage VT and

ID=K(VGS–VT)2
the proportional constant K are given in
the E-MOSFET transistor data sheet.

 The K is a property of the device

construction.

0V V V (V)
T GS
(a) Transfer Characteristic
 Transfer characteristic of E-MOSFET (VGS – ID)

VGSON ,IDON and VT are ENMOSFET parameters, Value “K” in the I D equation
can be found from these three parameters.

ID  K VGS  VT 2
where K is given by IDON  K VGSON  VT 2

Example:
ENMOSFET parameters are IDON=10mA,
VGSON=8V and VT=2V and
Find ID if VGS=+5V
10mA  K 8V  2V 2  K  10
36
ID  10 5V  2V 2  10  9   2.5mA
36 36

90
 E-MOSFET characteristic and parameters
 E-MOSFET is a voltage-controlled current device.
 Unlike the BJT where the collector current IC is related to the base current IB by the
dc beta value DC, the E-MOSFET drain current ID is not related to its gate-to-source
voltage VGS in that simple way.
 Let consider the E-MOSFET circuit shown and set the gate-to-source voltage VGS >
VT , and then vary the d.c. voltage VDD to observe the changes in drain-to-source
voltage VDS and the drain current ID.
ID
RC
Ammeter
mA B VGS1
_ ID1 C Breakdown
+
Saturation Region
ID + Region
+
VDD
VDS Linear Region
V
+ + _ (Triode/Ohmic
_ Region)
VGG V VGS Voltmeter
_ Constant Current
_
Region or
Active Region
0A VDS
VDS(Sat) (Saturation voltage)
 E-MOSFET characteristic and parameters (cont’d)
 The induced n-channel in the p-substrate does not become sufficiently conductive to
allow drain current to flow until VGS reach a certain threshold voltage (VT).
 As VDS increases from zero (by increasing VDD), the drain current ID increases
proportionally initially until it reaches certain value (at point B).
 During this region, the channel resistance between the drain and the source terminals
is essentially constant.
 The drain current ID increases linearly with VDS. This is known as the Ohmic region
because in this region VDS and ID are related by the Ohm’s law.
 Sometimes, this operating region is also known as the voltage-control-resistance
region where the channel resistance RDS is controlled by the gate-to-source voltage
VGS.

ID

Source Gate Drain

B VGS1 C Breakdown
Terminal Terminal Terminal ID1
Saturation Region
Metal Region
SiO2 Contact
Linear Region
(Ohmic Region)
n-doped
material Induced n-Channel
p-substrate Constant Current
Region or
Active Region
n-channel Enhancement-type MOSFET VDS
0 A
VDS(Sat) (Saturation voltage)
 E-MOSFET characteristic and parameters (cont’d)
 As VDS continue to increase further, the channel becomes narrower at the
drain end. This narrowing occur because the VGD becomes smaller when
VDS becomes larger (because VGD = VGS – VDS), thus reducing the positive
field at the drain end.
 As a consequence, the resistance of the channel begins to increase, and
drain current begins to level off.
 This leveling off occur when VGD = VT. That is, the positive voltage at the
drain end reaches the threshold voltage and the channel width at the drain
end shrinks to zero.
 Further increases in VDS do not change the shape of the channel and
current ID does not increase any further (i.e. ID saturates).
 The drain-to-source voltage VDS at which the drain current first becomes
constant is known as the saturation voltage, VDS(sat) .
VDS(sat) = VGS – VT
 The operating region after VDS(sat) occurs is known as the constant-current
region or the active region or the saturation region.
 Operating Limits of MOSFET
 Similar to the BJT, Field Effect
Transistors are limited by its allowable
operating rating such as:
I D ( mA)
- the maximum continuous drain
current ID(max);
I D(max)
- the maximum drain-to-source
voltage VDS(max), and
- the maximum power dissipation
PD(max) at the operating point P D(max)
= I Dx V DS
(Q-point).
 Note that the maximum power dissipation
PD(max) may not necessary equal to the
product of the maximum continuous
Safe Operating VDS(max)
drain current ID(max) and the maximum
drain-to-source voltage VDS(max) . Region
 For example, the n-channel E-MOSFET V (V)
DS
2N7008 has the following ratings on its
data sheet.
- VDS(max) = 60V,
- ID(max) = 150mA, and
- PD(max) = 400mW.
EN-MOSFET Summary

95
 Precautions in handling MOSFETS
1. MOS Integrated Circuits (IC) are made up of many transistors.
2. MOSFETs or integrated circuits have similar input characteristics.
3. The silicon oxide dielectric layer (for insulation between the gate terminal and the channel)
has a natural high impedance (or resistance) and are very sensitive to high static voltage.
4. The amount of electrical charges or static charges we carry on our body can destroy or
puncture the insulation layer.
5. Once it is punctured, current will flow between the gate terminal and the source terminal.
6. The MOSFET will then lost its transistor property.
7. The following precautions are necessary when handling MOSFETs:
--Keep all the leads shorted (or tie together).
Manufacturers usually supply a metal ring on the device.
--Pick up the device by the case and not the leads.
--Never insert or remove device with the power on.
--Transport or store them in closed conductive containers.
--Ground (or earth) yourself with a conductive material before
handling MOSFET devices. This reduces your body potential
(or static charges) to zero.
>>????

97
 Enhancement and Depletion MOSFET
 Enhancement — the channel is originally not
conducting when gate voltage is 0, and we
have to apply a positive gate voltage (bigger
than a threshold Vth or VT) to make it conduct
(enhance it).

 Depletion — In fact, we also have another

kind of MOSFET, in which the channel can
conduct even when gate voltage is not
applied. Then, we need to apply reverse gate
voltage to cut it off. This is called depletion
MOSFET.

 NOTE THAT DUE TO A SEMICONDUCTOR

DOPING PROPERTY:
 For n-channel MOSFET, both enhancement and
depletion types can be made.
 For p-channel MOSFET, only enhancement type can
be made.
 Depletion MOSFET
 Also called MOSFET
 Two Depletion MOSFET: n-channel and p-channel

n-channel MOSFET p-channel MOSFET

n-channel MOSFET p-channel MOSFET

n-channel MOSFET
characteristic

100
 JFET and MOSFET VGS – ID characteristics

D ID D ID
G
n-channel JFETVGS VDS VGS
G
VDS n-channel MOSFET
S S

Because of pn
junction at Gate to
Source, n-channel
JFET is capable of
operating at only
negative VGS
Because of Metal
oxide layer between
Gate to Source n-
channel MOSFET is
capable of operating
with positive VGS

Both JFET and MOSFET (Depletion MOSFET) has similar characteristics as shown
above except that MOSFET can operate with positive V GS 101
 JFET and MOSFET
Mathematical VGS – ID equation
Note that when VGS= 0, ID= IDSS and also when VGS= Vp, ID= 0

Two important FET parameters IDSS (Drain

current Source Shot-circuited) and Vp (pinch-off
voltage)

Example:
JFET parameters are IDSS =8mA and Vp=(-
4)V Find ID if VGS=-1V
2 2
 VGS    1V 
ID  IDSS  1    8mA 1 
   4.5mA
 VP    4V 
102
 VGS – ID characteristics of
JFET, MOSFET, and ENMOSFET
n-channel MOSFET n-channel ENMOSFET
n-channel JFET

103
 Biasing of FET
1. N-channel FET biasing circuits
2. MOSFET biasing circuits
3. FET biasing circuit analysis
4. ENMOSFET biasing circuit

104
 FET amplifier biasing design

Biasing methods
VDD VDD
RD RD

RS RL RS RL
RG RG

Self bias FET circuit

VDD VDD
RD RD
R2 R2

RS RL RS RL
R1 R1

Voltage-divider bias FET circuit

 Biasing of FET
1. n-channel FET biasing circuit

n-channel JFET n-channel MOSFET n-channel ENMOSFET

D ID D ID D ID
G
G G
VGS VDS VGS VDS VGS VDS
S S S

2 2
 V 
ID  IDSS  1  GS   V 
ID  IDSS  1  GS  ID  K VGS  VT 2
 VP  VP 


JFET and MOSFET are normally ENMOSFET is normally used as

used as voltage amplifier CMOS pair in power amplifier
and digital gate
106
JFET biasing circuit
VDD VDD
+
+ RD
RD R1 IDRD
ID R D ID
ID -
IG=0 - IG=0 +
+ 2 VG
 V  VDS
+ VDS ID  IDSS  1  GS 

V +
VP  -

GS
S
VG - -  R2 +
RG

-
+ RS
RS
IDRS IDRS
-
-

JFET self-bias JFET voltage-divider bias

IGRG  0  VGS  IDRS RR
RG  R1 // R2  1 2
R1  R2
R2 R R
VG  VDD  1  VDD G
R1  R2 R1 R1
VG  VGS  IDRS

107
2. MOSFET biasing circuit
JFET and MOSFET are analyzed exactly in the same way, except V GS
which can be positive in MOSFET
VDD VDD
+
+ RD
RD R1 IDRD
ID R D ID
ID -
IG=0 - IG=0 +
+ 2 VG
 V  VDS
+ VDS ID  IDSS  1  GS 

V +
VP  -

GS
S
VG - -  R2 +
RG

-
+ RS
RS
IDRS IDRS
-
-

MOSFET self-bias MOSFET voltage-divider bias

IGRG  0  VGS  IDRS RR
RG  R1 // R2  1 2
R1  R2
R2 R R
VG  VDD  1  VDD G
R1  R2 R1 R1
VG  VGS  IDRS

108
3. FET biasing analysis
Example:
Following JFET parameters are VP=-6V,IDSS=12mA. FET circuit has
VDD=12V, RG=1MW, RD=1.5kW, RS=1kW. Find Drain current ID and FET
terminal voltages VGS, and VDS.
2 2 VDD
 V    IDRS 
ID  IDSS  1  GS   12 1  I in mA and RS in k
 VP    6  D RD
+
IDRD
2 ID

 12 1 

 ID  1 
6   
12
36

3

 6  ID 2  1 36  12ID  ID2  12  4ID  0.33ID2 IG=0 -
+
+ VDS
a  0.33, b  5, c  12  quadratic equation S -
VG -
 ( 5)  25  4  0.33  12 5  3.026 RG +
ID    12.16mA,& 2.99mA RS
2  0.33 0.66 IDRS
VGS  IDRS  12.16  1  12.16V  6V(VP ) is neglected  ID  2.99mA -

VGS  IDRS  2.99mA  1k  2.99V

VDS  VDD  IDRD  IDRS  12  2.99  1.5  2.99  1  4.525V

109
 Example:
Given the characteristics of the JFET and it’s circuit, (a) find parameters
VP and IDSS. (b) FET circuit has VDD=12V, RG=1MW, RD=1.5kW, RS=1kW. Find
Drain current ID and FET terminal voltages VGS, and VDS.

VDD
+
RD
IDRD
ID
-
IG=0 +
+ VDS
S
VG - -
RG +
RS
IDRS
-

( a) IDSS  10mA & VP  8V

(b) Plot the line VGS  IDRS

(1) VGS  0V, ID  0mA (2) VGS  4V, ID  4V / 1k  4mA

Cros sin g Po int at VGS  3.2V and ID  3.2V / 1k  3.2mA  Ans.

VDS  VDD  ID RD  RS   12  3.2mA  2.5k   4V

110
Example:
Following JFET has IDSS=8mA. FET circuit has VDD=18V, VD=9V R1=750kW,
R2=91kW, RD=2kW, RS=0.68kW. Find Drain current ID and FET terminal voltages
VS, VG,VGS,VDS and FET parameter VP

18  9 VDD  18 V
( a) ID   4.5mA
2k
(b) VS  IDRS  4.5x0.68  3.06V
2 k
R2 18x91k 750 k  ID
(c) VG  VDD   1.95V VD  9 V
R1  R2 750k  91k
+ I
(d) VGS  VG  VS  1.95  3.06  1.11V VG DSS  8 mA
VDS
VP  ?

V +
VGS  1.11

S
V -

G
Vp     1.48V S

-
ID 4.5mA 91 k 
1 1 0.68 k 
IDSS 8mA
(e)VDS  VD  VS  9  3.06  5.94V

111
Example:
Following MOSFET has IDSS=8mA. VP=-4V
FET circuit has VDD=18V, VD=9V R1=750kW, R2=100kW, RD=2kW. Find Drain
current ID , RS and FET terminal voltages VS, VG,VGS,VDS.

V  VD VDD
RG  750k // 100k  88.24k and ID  DD +
RD RD
R1 IDRD
2 2 ID
18  9  VGS   VGS  -
ID   4mA  IDSS  1    8 1 
 
2k  VP    4  IG=0 +
VG VDS
VGS 4

V +
1  VGS  4  0.293   1.172V -

GS
4 8
R2 +

-
R 88.24k RS
VG  VDD  G  18   2.12V  VGS  IDRS IDRS
R1 750k
-
V  VGS 2.12  ( 1.172)
RS  G   0.823k
ID 4mA
VS  IDRS  4  0.823  3.392V
VDS  VD  VS  9  3.392  5.7V

112
4. ENMOSFET biasing circuit
n-channel ENMOSFET

D ID

G
VGS VDS
S

ID  K VGS  VT 2

IDON  K VGSON  VT 2 
K is found from parameters IDON , VGSON , VT
then plot ID & VGS curve

113
 ID = ?

IDON=10mA, VGSON=8V and VT=2V

D ID

G
VGS VDS
S

VGS=+5V

Example:
ENMOSFET parameters are IDON=10mA, VGSON=8V and VT=2V and
Find ID if VGS=+5V
10mA  K 8V  2V 2  K  10
36
 
ID  10 36 5V  2V 2  10  9 36  2.5mA

114
Example:
Following ENMOSFET has IDON=10mA, VGSON=8V and VT=2V, (a) find K.
(b) If VDD=12V, RD=2kW, RG=10MW. Find Drain current ID and FET terminal
voltages VG,VGS,VDS.

( a) ID  K VGS  VT 2
10mA  K 8V  2V 2  K  10
36

(b) Plotting of ENMOSFET characteristics and Plotting of ENMOSFET Drain

circuit with RD=2k and find the crossing point to get V GS -----continue…..

115
Solution:
(a) Plotting of ENMOSFET having I DON=10mA, VGSON=8V and VT=2V

ID  K VGS  VT 2
10mA  K 8V  2V 2  K  10
36
 ID  10 36 VGS  2V 2
Substituting VGS we have ID point s as follows

VGS 8V 6V 5V 4V 3V

ID 10m 4.5m 2.5m 0.3m

1mA
A A A A

116
(b) Plotting of ENMOSFET Drain circuit with R D=2k

ID=3.4mA

VDS=5.5V

VG=5.5V

From Drain circuit ,

IG  0  VG  VGS  12V  ID  2k
12  VGS
ID 
2k
If VGS  4V, ID  4mA
If VGS  8V, ID  2mA
Cros sin g poit is at VGS  5.5V  Ans

 ID  10 36 VGS  2V 2  10 36 5.5  2V 2  3.4mA

117
Example:
Given the characteristics of ENMOSFET below, (a) find K and V T
(b) If VDD=12V, RD=2kW, RG=10MW. Find Drain current ID and FET terminal
voltages VG,VGS,VDS.

( a) Take ID (on )  6mA, Then VGS (on )  8V, VTh  3V

6
6  K 8  32  K   0.24  Ans
25

(b) From Drain circuit ,

IG  0  VG  VGS  VDS
But VDS  12V  ID  2k
12  VGS
ID   Plot on the graph
2k
If VGS  6V, ID  3mA,
If VGS  9V, ID  1.5mA,
this line crosses the curve at VGS  6.2V  VG
12  VGS 12  6.2
ID    2.9mA  Ans
2k 2k

118
 Modeling of FET

• FET Equivalent circuit

• Parameter gm
• Amplifier equivalent circuits

119
 FET Equivalent circuit
n-channel JFET

2
 V 
D ID ID  IDSS  1  GS 
 VP 
G
VGS VDS
S Note that JFET and MOSFET have
their parameters VP and IDSS

In the characteristics of the FET,

n-channel MOSFET
Change in Drain current ID will be
produced by a change in VGS(VGS)
D ID according to FET equation
2
 V 
G ID  IDSS  1  GS 
 VP 
VGS VDS
S

120
Note also that Gate current I G=0 in FET

Change in Drain current ID with respect to a change in VGS(VGS) is called

transconductance parameter g m of the FET
ID Id
gm   ID  gm  VGS  Id  gmVgs
VGS Vgs

121
 Parameter gm
10.2.1 Graphical value

Note that gm
becomes smaller
ID 2.1mA
when ID is less gm1    3.5mS
VGS 0.6V

ID 1.8mA
gm2    2.57mS
VGS 0.7V

ID 1.5mA
gm3    1.5mS
VGS 1V

122
Mathematical value

 2
ID dID
d   V 
gm    IDSS 1  GS 


VGS dVGS dVGS   VP  
 
2
d  V 
 IDSS 1  GS 
dVGS  VP 

 V  d dV 
 2IDSS 1  GS   1  1 GS 
 VP   dVGS VP dVGS 
 V  1
 2IDSS 1  GS  0  
 VP   VP 
2I  V 
 DSS 1  GS 
VP  VP 

2IDSS  V 
or gm  1  GS 
VP  VP 

 V  2I
or gm  gm0 1  GS  where gm0  DSS
VP  VP
 

123
 Analysis of Self-Bias Amplifier
VDD VDD
+
RD
IDRD RD
ID Id
- ID Vo
IG=0 + Vo
+ Vin
VDS Vin
+ VDS
- S
- RD
RG VG - RG
RS RG RS
RS CS

JFET self-bias JFET self-bias amplifier Amplifier ac equivalent circuit

D
Vo
G
Vin gmVgs
+V
g s-
RD
S
RG Ro
Rin RS

124
self-bias amplifier equivalent circuit
 D
Vo ac analysis
G
Vin gmVgs Rin  RG
+V
g s-
RD Ro  RD
S
Rin
RG
RS Ro AV 
Vo

 
 gmVgs  RD 
 gmRD
Vin Vgs

• Self bias amplifier has a high voltage gain.

• Output resistance is RD

125
Example:
Find the AV , Rin , Ro of the given Self-Bias FET amplifier including FET
output resistance rd=100k
VDD

3.3kW
IDSS= 8mA I
Vp= -6V
D
Vo
Vin
+
S
VG - Ro
1MW
1kW CS 2.6mA
Rin

-2.6V
V
dc analysis  VGS  IDRS  GS  ID
1k
Two point s for this equation
1  VGS  0, ID  0
2  VGS  4V, ID  4mA
Jo int them on FET graph. Cros sin g point is VGS  2.6V
2IDSS  VGS  2  8   2.6V 
Get gm  gm  1   1   1.51mS
VP  VP   6   6V  126
 VDD

3.3kW
D
IDSS= 8mA I Vo
Vp= -6V
D
Vo G
Vin gmVgs
Vin +
+ RD
GS
Vgs
V - Ro RG - rd
1MW Ro
1kW CS S
Rin Rin

ac analysis
Rin  RG  1M
Ro  RD // rd  3.3k // 100k  3.19k

AV 
Vo

 
 gmVgs  3.3k // 100k 
Vin Vgs
 1.51mS  3.19k   4.82

127
128
 FET Amplifiers
 There are three basic types of FET amplifiers.
(1) Common-Source Amplifier,
(2) Common-Drain Amplifier, and
(3) Common-Gate Amplifier.
 The study of n-channel E-MOSFET in this chapter will be focus on common-source
amplifier.
 Common-source amplifier is a general purpose amplifier.
 The input ac signal is applied to the gate terminal.
 The output ac signal is taken from the drain terminal.
 The source is grounded through a source capacitor CS as reference.

R1 RD
CD
vout VDD
CG D +
G

S
RL
vin
R2
Cs RS

Common/Ground
 DC analysis on Q-point calculation
 As IG=0, The gate voltage is given by the following expression:
VG = (R2 VDD) / (R1 + R2)
 Applying KVL around the gate terminal loop, we have:
VG = VGS + RS ID
 Apply KVL on output loop, VDSQ=VDD–IDQ(RD+RS)
when RS=0, VDSQ=VDD–IDQRD

Voltage divider bias CS DC equivalent circuit

amplifier
VDD

R1 RD R1 RD
CD
vout VDD ID
CG D +
G D
G
S
RL +
S
vin
R2
VGS -
Cs RS R2 RS

Common/Ground
 DC analysis on Q-point calculation (cont’d)
 From VG = VGS + RS ID , the bias line equation can be derived as:
ID = (VG –VGS) / RS -- Bias line equation
If RS=0, then bias line equation becomes: VGS=VG

 Plot E-MOSFET transfer characteristic ID = K (VGS – VT)2 and the bias line equation ID = (VG
–VGS) / RS , we can determine the Q-point on the transfer characteristic co-ordinates.

When RS 0 When RS= 0

Transfer ID Transfer
Characteristic: Characteristic:
ID
ID = K(VGS – VT )2 ID = K(VGS – VT )2

DC Bias line DC Bias line

IDQ ID = (VG –VGS) / RS IDQ Q
Q VGS =VG

VT VGSQ VG VGS VT VGSQ=VG VGS

 FET amplifier example (***)
A FET common-source amplifier is shown below. The threshold voltage of E-MOSFET
is 3V, when VGS =8V, the drain current is 5mA.
(a) Find K and VGSQ
(b) Sketch transfer characteristic of the E-MOSFET for 3V  VGS 10V
(c) Sketch the bias line on the transfer characteristic
(d) Determine IDQ and VDSQ
Solution:
Draw dc equivalent circuit:
+VDD=20V VDD 20V
RD 2.2KΩ
R1
52KΩ RD
vout R1
2.2KΩ
CG D 52k
G CD ID

D
S
RL VG G
vin 50KΩ
+ S
R2
R2 VGS -
22KΩ
22k

Common/Ground
 FET amplifier example (***) (cont’d)
Step 1: find K from ID = K (VGS – VT)2 Step 4: plot the transfer
characteristic
K=ID/(VGS–VT)2 =5mA/(8–3)2=0.2mA/V2
Step 5: sketch bias line on transfer
Step 2: find VGSQ characteristic
VGSQ=VG=R2VDD/(R1+R2) VGS = VG = 5.95V
=2220/(22+52)=5.95V --- Bias line equation
Step 3: calculate ID with assumed values of VGS based Step 6: Determine IDQ, VDSQ
on transfer characteristic. IDQ=K(VGSQ–VT)2
ID = (0.2mA/V2) (VGS –3V)2 =0.2mA(5.95–3)2=1.74mA
VDSQ=VDD–IDQRD
VGS(V) ID (mA )
=20–1.74mA2.2KΩ=16.17V
3 0
12 ID
Transfer
4 0.2
10 characteristics
5 0.8 IDQ=K(VGSQ-VT)2
8
6 1.8
Bias line
6
7 3.2 VGS=VG
4
8 5
9 7.2 2
IDQ Q
10 9.8 0
0 2 4 6 8 10 12
VGSQ VGS
 Small-Signal Equivalent Circuit of MOSFET
• The small-signal ac equivalent model is shown below.

Gate Drain

vgs rgs gm vgs vds

Source Source

 In analyzing ac signal, the small-signal drain current id of a MOSFET can be

calculated from the small-signal equivalent circuit of the transistor circuit.
 The gate-to-source resistance rgs is usually very large because the gate-to-
channel junction (or the gate-to-source) is always insulated in the case of
MOSFET.
 Therefore, the gate-to-source is represented by an open-circuit rgs = very large.
Small-Signal Equivalent Circuit of MOSFET (cont’d)
Gate Drain

vgs rgs gm vgs vds

Source Source
ID

gm = id / vgs
gm varies depending on the bias
Q point (Q-point)
id
vgs
VGS
VT
 The transconductance gm is the gradient at the Q-point on the transfer
characteristic curve. It is expressed by the following equation.
gm = id / vgs (siemens)
 Common source (CS) amplifier employing an
V
E-MOSFET
DD D vout
RD G
R1 CD
VD vout +
vgs S
Co _ RD RL
VG vin R RG =R1//R21
+ ID
VGS _
VS RL
vin R2
Load
Cs Rs Resistance
AC signal equivalent circuit
id
Common-source amplifier D vout
G
 To obtain CS amplifier ac equivalent +
+
circuit, we replace VDD with ground and
replace all capacitors with wire. RL // RD
vin RG vgs gmvgs
 Replace the E-MOSFET with its small-
signal ac model, we can obtain its _
_
small-signal ac equivalent circuit.
S
Small signal ac equivalent circuit
Common source (CS) amplifier employing an
E-MOSFET (cont’d)
 From the small-signal ac equivalent circuit, we can derive the following values of the common-
source amplifier.
 Input resistance rin = RG = R1 // R2 ,

 Output resistance rout = rac = RD // RL,

 Voltage gain AV = vout / vin = – gm (RD // RL)

 The gradient (or slope) of the ac load line is equal to rac = RD // RL.
(Note that the gradients of the dc loadline and the ac loadline are different.)
id
D vout
G
+
+

RL // RD
vin RG vgs gmvgs

_
_

S
Small signal a.c. equivalent circuit
 VDD
Example
RD
Determine the input resistance, output R1 CD
resistance and the voltage gain of the VD vout
common-source amplifier. The E-MOSFET Co VG
is biased at VDSQ = 15V & IDQ = 10mA + ID
VGS _
having a transconductance gm = 15ms. VS RL
The resistances used are: vin R2
Load
R1= 200k, R2= 200k , RD= 1k, and RL= Cs Rs Resistance
1k.

Solution Common-source amplifier

Input resistance id
rin = RG = R1 // R2 = 100k, D vout
G
Output resistance +
+
rout = rac = RD // RL= 1k // 1k
= 500, RL // RD
vin RG vgs gmvgs
Voltage gain
AV = vout / vin = –gm (RD // RL)
_
= –15ms x 500= – 7.5 _
The negative sign indicates that the output S
signal is 180O out of phase with the input
Small signal ac equivalent circuit
signal.
 Switching Application of E-MOSFET
 Other than employed in transistor amplifier, MOSFETs are also used in other
applications such as an electrical switch.
 Note that the MOSFET is said to be turn ‘ON’ when it is conducting and ‘OFF’ when it
is not.
 The MOSFET will conduct when VGS = +10V and will not conduct when the value of VGS
= 0V.
 Vin (V) VS (V) VGS = Vin - VS (V) MOSFET Vout (V)
+10 0 +10 ON 0
0 0 0 OFF +10
 Thus, when the input is +10V, the MOSFET will conduct (ON) and when the input is 0V,
the MOSFET will not conduct (OFF).
 The relationship between signals Vin and Vout are inverted.
VDD + 10V
RD

ID Vout= VDS= VDD– IDRD

D vout
G
+ S
vin VGS _
CMOS Inverter
CMOS NAND Gate
CMOS NOR Gate
 FET Small signal Analysis

• FET Small signal Analysis

• MOSFET Small signal Analysis

145
 Analysis of Self-Bias Amplifier
VDD VDD
+
RD
IDRD RD
ID Id
- ID Vo
IG=0 + Vo
+ Vin
VDS Vin
+ VDS
- S
- RD
RG VG - RG
RS RG RS
RS CS

JFET self-bias JFET self-bias amplifier Amplifier ac equivalent circuit

D
Vo
G
Vin gmVgs
+V
g s-
RD
S
RG Ro
Rin RS

146
self-bias amplifier equivalent circuit
 D
Vo ac analysis
G
Vin gmVgs Rin  RG
+V
g s-
RD Ro  RD
S
Rin
RG
RS Ro AV 
Vo

 
 gmVgs  RD 
 gmRD
Vin Vgs

• Self bias amplifier has a high voltage gain.

• Output resistance is RD

147
Example:
Find the AV , Rin , Ro of the given Self-Bias FET amplifier including FET
output resistance rd=100k
VDD

3.3kW
IDSS= 8mA I
Vp= -6V
D
Vo
Vin
+
S
VG - Ro
1MW
1kW CS 2.6mA
Rin

-2.6V
V
dc analysis  VGS  IDRS  GS  ID
1k
Two point s for this equation
1  VGS  0, ID  0
2  VGS  4V, ID  4mA
Jo int them on FET graph. Cros sin g point is VGS  2.6V
2IDSS  VGS  2  8   2.6V 
Get gm  gm  1   1   1.51mS
VP  VP   6   6V  148
 VDD

3.3kW
D
IDSS= 8mA I Vo
Vp= -6V
D
Vo G
Vin gmVgs
Vin +
+ RD
GS
Vgs
V - Ro RG - rd
1MW Ro
1kW CS S
Rin Rin

ac analysis
Rin  RG  1M
Ro  RD // rd  3.3k // 100k  3.19k

AV 
Vo

 
 gmVgs  3.3k // 100k 
Vin Vgs
 1.51mS  3.19k   4.82

149
 Analysis of Self-Bias with RS Amplifier
VDD

RD Id
Vo
ID Vo Vin
Vin +
+ VDS RD
GS
V - - RG
RG RS
RS

JFET self-bias with RS amplifier Amplifier ac equivalent circuit

D
Vo
G
Vin gmVgs
+V
g s-
S RD
RG Ro
Rin RS

self-bias amplifier with RS equivalent circuit 150

 D
Vo
G
Vin gmVgs
+V
g s-
S RD
RG Ro
Rin RS

ac analysis
Rin  RG
Ro  RD
V
AV  o 

 gmVgs  RD 


 gmRD
Vin Vgs  gmVgs  RS 1  gmRS

• Self bias with RS amplifier has a lower voltage gain.

• Output resistance is higher than R D due to current source.

151
Example:
Find the AV , Rin , Ro of the given Self-Bias FET amplifier.
20V

3.3kW
ID Vo
Vin
+
S
1MW VG -
Ro
1kW
Rin 2.6mA

-2.6V
V
dc analysis  VGS  IDRS  GS  ID
1k
Two point s for this equation
1  VGS  0, ID  0
2  VGS  4V, ID  4mA
Jo int them on FET graph. Cros sin g point is VGS  2.6V
2IDSS  VGS  2  8   2.6V 
Get gm  gm  1   1   1.51mS
VP  VP   6   6V  152
 20V
D
Vo
3.3kW G
Vin gmVgs
ID +V
Vo g s-
S 3.3kW
Vin 1MW
+ Rin Ro
GS
V - 1kW
1MW Ro
1kW
Rin

ac analysis
Rin  RG  1M
Ro  RD  3.3k
V
AV  o 
 
 gmVgs  3.3k   1.51  3.3k

Vin Vgs  gmVgs  1k 1  1.51  1k 
  1.985

153
 Analysis of Source Follower Amplifier
VDD

ID

Vin +
S
VG - Vo
RG Vin
RS
Vo
RG
Rin RS
Ro

Vin G gmVgs
+V
gs
- S
Vo
RG
Rin RS
Ro
154
 D Vin shorted to find RO

Vin G gmVgs G gmVgs

+V +V
gs gs Io
- S -
Vo Vo
RG RG
Rin RS RS
Ro Ro

ac analysis Ro  RS // Vo / Io 
Rin  RG
V 
 Vgs  1
Vo  
 gmVgs  RS  gmRS But o 
Io  gmVgs

gm
AV   
Vin Vgs  gmVgs  RS 1  gmRS
1
g R Ro  RS //
If 1  gmRS , AV  m S  1 gm
gmRS

• Source Follower amplifier has a voltage gain of approximately 1

• Output resistance is very low as it is nearly 1/g m

155
Example:
Find the AV , Rin , Ro of the given Source Follower FET amplifier.

20V

ID

Vin +
S
VG - Vo
1MW
1kW
Rin Ro
2.6mA

-2.6V
V
dc analysis  VGS  IDRS  GS  ID
1k
Two point s for this equation
1  VGS  0, ID  0
2  VGS  4V, ID  4mA
Jo int them on FET graph. Cros sin g point is VGS  2.6V
2IDSS  VGS  2  8   2.6V 
Get gm  gm  1   1   1.51mS
VP  VP   6   6V  156
 20V
D
ID
Vin G gmVgs
+V
gs
Vin + - S
S
VG - Vo
Vo RG
1MW Rin RS
1kW Ro
Rin Ro

ac analysis
Rin  RG  1M
V 
 gmVgs  RS  
gmRS 1.51  1k
AV  o     0.6
Vin Vgs  gmVgs  RS 1  gmRS 1  1.51  1k

Ro  RS // Vo / Io 
V 
 Vgs 1 
But o  
Io  gmVgs gm
1 1
Ro  RS //  1k //  1k // 0.662k  0.398k
gm 1.51
157
Analysis of Common Gate Amplifier
VDD

RD
Id
ID Vo
Vo

Vin RD
Vin
Ro RS Ro
RS
Rin
Rin

Vo

gmVgs
+ Vgs
- RD
Vin
Ro
RS
Rin

158
 Vo Vo

gmVgs gmVgs
+ Vgs + Vgs
- RD Iin - RD
Vin Vin -
- Ro IRS Ro
RS Vgs Vgs
+ RS
Rin Rin +

ac analysis ac analysis
Ro  RD Ro  RD
V
AV  o 
 gmVgs  RD  gmRD
  Vgs 1
Vin  Vgs Rin  RS //  RS //
 gmVgs gm

• Common Gate amplifier has a non-inverting high voltage gain.

• Input resistance is very low as it is nearly 1/g m

159
Example:
Find the AV , Rin , Ro of the given Common Gate FET amplifier.
12V

3.6kW

IDSS= 8mA ID
Vo
VP= -6V

Vin
Ro
1kW
Rin 2.6mA

-2.6V
V
dc analysis  VGS  IDRS  GS  ID
1k
Two point s for this equation
1  VGS  0, ID  0
2  VGS  4V, ID  4mA
Jo int them on FET graph. Cros sin g point is VGS  2.6V
2IDSS  VGS  2  8   2.6V 
Get gm  gm  1   1   1.51mS
VP  VP   6   6V  160
 12V

3.6kW

IDSS= 8mA ID Vo
Vo
VP= -6V
gmVgs
+ Vgs
- RD
Vin
Vin
Ro - Ro
RS Vgs
1kW
Rin +
Rin

ac analysis
Ro  RD
V
AV  o 

 gmVgs  RD  
 gmRD  1.51  3.6k  5.436
Vin  Vgs

 Vgs 1 1
Rin  RS //  RS //  1k //  1k // 0.662k  0.398k
 gmVgs gm 1.51mS

161
 FET Amplifier
Configurations and Design

162
 FET Amplifier
Configurations and Design

•Types of FET amplifiers

•FET characteristics
•FET Optimum Q point
•FET amplifier biasing design

•CS amplifiers and Design

•CS with RS amplifiers and Design
•SF amplifiers and Design
•Bootstrap amplifier and design
•CG amplifiers and Design
 Types of FET amplifiers (JFET)
VDD
VDD
Rac = RD//RL RD
Rdc = RD+RS Rac =( RD//RL)+RS RD
vo
Ri C2 C1 Rdc = RD+RS vo
Ri C2 C1
RL
vi RG RL
CS vi RG
RS
RS

(a) Common Source (CS)

High AV and high Ri (b) Common Source (CS) with R S
Voltage amplifications Low AV and high Ri
Stability applications
VDD VDD
Rac = RS//RL Rac =( RD//RL)+(RS//Ri) RD
vo
Rdc = RS Rdc = RD+RS
Ri C2 CG C1
C1 vo
RL
vi RG RL RG C 2 Ri vi
RS RS

(c) Source Follower (SF) (d) Common Gate (CG)

Very low Ro and high Ri Very low Ri and high AV
Buffer applications High Frequency applications
 FET characteristics

JFET and DEMOS FET analysis

D ID
G ID ID
IG=0 VDS JFET 7
VGS S I , V
DSS P
6 IDSS=6mA VGS= 0V
5
VP and IDSS are FET data 4 VGS= -0.5V
D ID 3
VGS= -1V
G DEMOS-FET 2
VDS
IG=0 1 VGS= -2V
I ,V
VGSS DSS P VGS 0 VGS= -3V
-3 -2 -1 0 0 4 8 12 16 VDS
-0.5
VP=-3V

• Both JFET and DEMOS-FET(Depletion MOSFET) has similar

characteristics as shown above.
• ID will conduct between two points defined by (ID = 0 when VGS = VP) and (ID
= IDSS when VGS = 0) 2
 V 
• ID will conduct according to the equation I D  IDSS 1  GS 

 VP 
 ENMOS FET analysis

VGSON ,IDON and VP are ENMOS-FET data

ID ID
7
ID 6
D VGS= 8V
5
I G= G VDS 4
0
VGSS IDON, VGSON,Vt 3
2 VGS= 6V
ENMOS-FET 1 VGS= 4V
0 VGS= 2V
VGS
0 2 4 6 VDS
Vt=2V
• ENMOS-FET is different from both JFET and DEMOS-FET and has the
characteristics as shown above.
• ID will conduct starting from the point defined by (I D = 0 when VGS = Vt )(Vt
is the transition frequency of ENMOS-FET)
• ID will conduct according to the equation ID  K VGS Vt 2
where K is given by I DON  K VGSON Vt 2
 FET Optimum Q point
• In BJT it is clipping that should be used to optimize for biasing the amplifier.
The optimum condition in the case of BJT is when I C = VCC / Rac +Rdc
• But in FET it is not clipping that should be used to optimize for biasing
the amplifier. The wave form will have harmonic distortion without
clipping because of non-linear characteristics of the FET (rounded top
but no top clipped). The optimum condition in the case of FET is when
operating in the linear region to avoid rounded waveform.
ID/IDSS
• The linear region is found from the slope of the 1.0
0.9
non-linear region of the FET characteristics by 1
0.8
plotting the equation:
I  V 
2
D
 1  GS 
I DSS  VP  0.6

0.5
• Linear region is around 0.4
(ID/IDSS)=0.5 which can be
0.2
substituted in the above equation
and get (VGS/VP)=-0.3 VGS/VP 0
-0.64
0
Design equation for optimum Q -1.0 -0.8 -0.6 -0.4 -0.2
-0.3
point of JFET and DEMOS-FET
 FET amplifier biasing design

Biasing methods
VDD VDD
RD RD

RS RL RS RL
RG RG

Self bias FET circuit

VDD VDD
RD RD
R2 R2

RS RL RS RL
R1 R1

Voltage-divider bias FET circuit

 Self bias FET circuit bias design
(JFET and DEMOS-FET)
VDD VDD

RD RD

+V +V
GS
-+ GS
-+
RS ID RL RS ID RL
RG RG
VRG - -

In the case of Self-bias FET circuit, R G

should be designed so that VRG is not
exceeding 10% of VP or IGSSxRG < 0.1VP

Biasing Design
IG=0 , VRG=0, VGS= - IDRS Self-bias VGS equation for self-
biasing of JFET
VDD=IDRD+VDS + IDRS Drain circuit KVL and DEMOS-FET
I
ID  DSS and VGS  0.3VP Optimum bias condition
2
 Voltage divider bias FET circuit bias design
VDD VDD
In the case of voltage-
RD RD VRG divider bias FET circuit,
R2 R2 by Superposition
theorem when VDD=0,RG
+ +V + + VGS + should be designed so
-+
GS
VG=VGG VG=VGG -
RS ID RL RS ID RL
that VRG not exceeding
R1 R1 CS 10% of VP or IGSSxRG <
- - - -
0.1VP

VDD=IDRD+VDS + IDRS KVL at Drain circuit VGG= VGS+ IDRS KVL at Gate circuit
I
I D  DSS and VGS  0.3VP Optimum bias condition
2
R R R1 R1 V R
RG  1 2 and ( I G  0 ) VGG  VDD or VGG  VDD  DD  1  2
R1  R2 R1  R2 R1  R2 VGG R1
R1 R R V R2 RG VDD / VGG RG
VGG  VDD  2  VDD G  R2  RG DD  R1   
R1  R2 R2 R2 VGG  VDD   VDD  V
  1    1  1  GG
V  V  VDD
 GG   GG 

R2 Design equation
R1 Design equation
 Summary of Design Equations
(dc design equations for all CS, CS with RS, SF, CG
V DD
configurations)
RD I Optimum IDQ Design equation
ID  DSS and VGS  0.3VP
2

+V 0.1VP RG Design equation

RG 
GS
-+ IGSS
RG RS ID
VGS  IDRS VGS Design equation for self-bias
-
V R
VGS  VGG  IDRS Where VGG  DD 1 VGS Design equation for Voltage
R1  R2
Divider bias
VDD V
R2  RG DD R2 Design equation
VGG
RD
R2 RG
R1  R1 Design equation
VG 1  VGG / VDD 
+V
-+
GS
R1 RS ID Vo (pp)  2  IDQ Rac Vo(pp) Design equation

-
Example

Draw and Design the value of R G ,RS and RD = RL for VD=VDD/2 of a JFET self-bias
amplifier circuit if the FET data is I GSS=200nA, IDSS=5mA and VP=-3V. Take VDD = 12V

0.1VP 0.3 VDD

I GSS RG  0.1VP  RG    1 .5 M 
I GSS 200  10 9
RD
Optimum I D  I DSS / 2   5 mA / 2   2.5 mA
Optimum VGS  0.3VP  0.3  ( 3 )  0.9V
0.9 +V
VGS  0.9V  I D RS  RS   0.36k  360 
-+
GS
2.5 mA
RG RS ID RL
12  12 2 
I D RD  VDD VD  RD   2.4 k -
2.5 mA
Example

Draw and Design the data IDSS and VP required if RS = 100W, VDD = 12V
for an DEMOS-FET self-bias amplifier circuit if R D = RL = 1kW to have VD=VDD/2 .

12  12 2   VDD
I D RD  VDD VD  I D   6 mA
1 k
RD
Optimum condition I D  IDSS / 2 
 I DSS  2 I D  2  6 mA  12 mA
+V
Optimum VGS  I D RS  0.3VP GS
-+
 I D RS  6 mA  0.1 k RG RS ID RL
VP     2V
0.3 0.3 -
Example
Draw and Design the value of R 1, R2, and RD = RL to have VD=VDD/2 of a JFET voltage
divider bias amplifier circuit if the FET data is I GSS=300nA , IDSS=5mA and VP=-3V.
Available VDD = 12V and specified RS = 1000W

0.1VP 0.3
I GSS RG  0.1VP  RG    1 M
I GSS 300  10 9

Optimum I D  I DSS / 2   5 mA / 2   2.5 mA

Optimum VGS  0.3VP  0.3  ( 3 )  0.9V VDD

12  12 2   RD
I D RD  VDD VD  RD   2.4 k R2
2.5 mA
 VGG  VGS  IDRS  0.9  2.5mA  1k  1.6V + + VGS +
VG=VGG -
V 12 RS ID RL
R2  RG DD  1M  7.5M R1
VGG 1 .6 -
-
RG 1M
R1    1.154M
VGG 1 .6
1 1
VDD 12
 Transconductance gm of FET
D D
G
G gmvgs
IDSS, VP vgs
VGS S
S
gm is an ac parameter of FET which is the rate of change of I D
with respect to VGS given by gm= diD/dvGS
2
 v 
For JFET or DEMOSFET, iD  IDSS  1  GS 
 VP 
2
diD d  v  2I  VGS   V 
 gm   IDSS  1  GS    DSS 1 

  gm0  1  GS 
dvGS dvGS  VP  Vp  VP  
 VP 
2
v 
For ENMOSFET iD  K VGS  Vt 2  KVt2  GS  1 
 Vt 
2
d 2  vGS  2KVt2  v 
 KVt   1     1  GS   gm  2K Vt  VGS 
dvGS  Vt  Vt  Vt 
K is given by IDON  K VGSON  Vt 2
 FET amplifier parameter gm
VDD
VDD
RD RD
R1
ID
ID
VG
IDSS VP gm
IG=0 + IDSS VP gm + +
VGS - VGS
RG + R2 - +
RS IDRS RS ID RS
- - -
JFET-self-bias amplifier JFET-voltage divider-bias amplifier

VGS  ID RS (self bias ) or VGS  VG  ID RS (voltage divider bias )    (1)

R1
Where VG  VDD (all components are given in the circuit )
R1  R2
2 2
 V    ID RS 
ID  IDSS  1  GS
  IDSS  1 
 
    (2)

 VP
  V P 
Substitute given IDSS , VP , RS in (2) above and get ID
Substitute ID in (1) and get VGS    (3)
 2IDSS  VGS 
Find gm  1 

 for FET equivalent circuit calculatio ns

VP  VP 
 VDD
RD
Example: Find gm of the given JFET amplifier
ID gm=?
IDSS=8mA
VP=8V

RG
RS=2.4k

V p  8V , I DSS  8mA, RS  2.4k but VGS  I D RS  2.4I D

2 2
 V    2.4I D  8
 ID  I DSS  1  GS   8 1 
    8  2.4ID 2
 VP   8  64
8I D  64  5.76ID2  38.4I D  5.76ID2  46.4ID  64  0
  46.4   2153  1474.6 46.4  26.04
ID    1.77 or 6.29
11.52 11.52
VGS   1.77mA  2.4k   4.25V or  6.29mA  2.4k   15.1V
But VGS  15.1V beyond VP  8V  neglected
 2I DSS  VGS  28  4.25 
 gm  1 


  1    0.94mS
VP  VP   8   8 
 CS amplifier and Design
VDD
RD

RL JFET-self-bias CS amplifier
RG
RS CS

VDD
RD
R2

JFET-v.divider-bias CS amplifier
RL
R1
RS CS

DMOS-v.divider-bias CS amplifier
 CS amplifier analysis
Ri iin ig=0 D
G vo
gmvgs
vgs iL
RG S
vin RD RL
vi CS amplifier equivalent circuit
Ro
Rin

Rin = RG Ro = RD

vo  gmvgs  RD // RL 
Av    gm (RD // RL )
vin vgs

I
Since ID  DSS and VGS  0.3Vp for Opt ID of JFET and DEMOSFET
2
 2IDSS  V   2ID / 2  0.3VP  I
 Opt. point gm   1  GS   1    1.42 DSS
VP  VP  VP  VP  VP
 
 Summary of Design Equations
(in addition to dc design equations for CS configuration)
VDD VDD
RD RD
R2

Circuits RL RL
RG R1
RS CS RS CS

Input / output resistance Rin = RG Ro = RD

I
Optimum gm  Opt. point gm  1.42 DSS
VP

Voltage gain Av  gm (RD // RL )

 Example

Draw a JFET self-bias CS amplifier circuit and design the value of required
RG , RS , RD = RL and VDD . FET data is given as IGSS=1mA, IDSS=5mA and VP=-3V,
The required specification is VD=VDD/2 and Av = -12

0.1VP 0.3 VDD

RG    0.3 M  300 k
I GSS 1 A
RD
I 5 mA
Opt . gm  1.42 DSS  1.42  2.367 mA / V 
VP 3
12 RL
Av   g m ( RD // RL )  12  RD  RL  2 k  10.13 k RG
2.367
RS CS
Opt . I D  I DSS / 2   5 mA / 2   2.5 mA
Opt . VGS  0.3VP  0.3  ( 3 )  0.9V
0.9
VGS  0.9V  I D RS  RS   0.36k  360 
2.5 mA
V
VDD VD  I D RD  DD  2.5 mA  10.13 k
2
VDD  50.65V
CS with RS amplifier and Design
VDD
RD

RL JFET-self-bias CS with RS amplifier

RG
RS

VDD
RD
R2

RL
R1
JFET-v.divider-bias CS with RS amplifier
RS

DMOS-v.divider-bias CS with RS amplifier

 CS with RS amplifier analysis
Ri iin ig=0 G D
gmvgs vo
vgs iL
RG S
vin RD RL
vi
RS Ro CS with RS amplifier equivalent circuit
Rin

Rin = RG Ro = RD

vo  g mv gs  RD // RL   g m ( RD // RL )
Av   
v in v gs  g mv gs RS 1  g m RS
 ( RD // RL )
 if 1  gm RS 
RS approximate
 Summary of Design Equations
(in addition to dc design equations for CS with RS configuration)

VDD VDD
RD RD
R2

Circuits RL RL
RG R1
RS RS

Input / output resistance Rin = RG Ro = RD

I
Optimum gm  Opt. point gm  1.42 DSS
VP

 gm (RD // RL )
Av 
Voltage gain 1  gmRS
 (RD // RL )
 if 1  gmRS 
RS
Example 1

Draw JFET self-bias CS with RS amplifier circuit and design the value of
required RG , RS , RD = RL and VDD of a if the FET has IGSS=1mA, IDSS=5mA and
VP=-3V. The required specification is VD=VDD/2 and Av = -2

Opt . I D  5 mA / 2   2.5 mA & Opt . VGS  0.3  ( 3 )  0.9V VDD

0.9 RD
VGS  0.9V  I D RS  RS   0.36k  360 
2.5 mA
I 5 mA
Opt . gm  1.42 DSS  1.42  2.367 mA / V 
VP 3 RL
RG
 gm (RD // RL )  (RD // RL )  2.36 RS
Av   2 
1  gmRS 1  2.36  0.36k
(RD // RL )  1.567k  RD  RL  2  1.567k  3.134k
VDD
VDD  VD  IDRD   2.5mA  3.134k  VDD  15.67V
2
0.1VP 0.3
RG    0.3 M  300 k
I GSS 1 A
Example 2

Draw JFET voltage-divider bias CS with RS amplifier circuit and design the
value of required RG , RD = RL and VDD if the FET has IGSS=1mA, IDSS=5mA and
VP=-3V,Take RS =360W. The required specification is VD=VDD/2 and Av = -2

VDD
Opt . I D  5 mA / 2   2.5 mA & Opt . VGS  0.3  ( 3 )  0.9V RD
R2
I 5 mA
Opt . gm  1.42 DSS  1.42  2.367 mA / V 
VP 3
RL
R1
 gm (RD // RL )  (RD // RL )  2.36
Av   2  RS
1  gmRS 1  2.36  0.36k
(RD // RL )  1.567k  RD  RL  1.567k  2  3.134k

RS is given to find VGG in

VDD
VDD  VD  IDRD   2.5mA3.13k   VDD  15.67V voltage-divider bias FET
2

0.1VP 0.3 VGG  VGS  IDRS   0.9  2.5mA  0.36k  0V

RG    0.3 M  300 k
I GSS 1 A
RG 300k
R1    300k
V 15.67 VGG 0
R2  RG DD  300k  (open) 1 1
VGG 0 VDD 15.67
 SF amplifier and Design

VDD VDD VDD

R1 R1

RG
RS R2 R2
RL RS RL RS RL

JFET-self-bias SF amplifier JFET-v.divider-ias SF amplifier DMOS-v.divider-bias SF amplifier

 SF amplifier analysis

Rin = RG
SF amplifier equivalent circuit
vo gmvgs  RS // RL  g (R // RL )
Av    m S Ri iin ig=0 D
vin vgs  gmvgs RS // RL  1  gm RS // RL  G
gmvgs
 1  if 1  gm RS // RL  vgs
RG S
vin vo
vi
RS RL
VRS  v gs and I RS  g mv gs  Ro  RS // VRS / I RS 
 
 RS // v gs / g mv gs  RS // 1 / g m  Rin Ro
Rin = RG Ro = RS//1/gm
 vin v
Example: Find Ro , Rin  , Av  o of the folowing SF amplifier .
iin vin

V p  8V , I DSS  8mA, RS  2.4k but VGS  I D RS  2.4I D VDD

2 2
 V    2.4I D  8
 ID  I DSS  1  GS   8 1 
    8  2.4ID 2
 VP   8  64 Vin IDSS=8mA
8I D  64  5.76ID2  38.4I D  5.76ID2  46.4ID  64  0 VP=8V

  46.4   2153  1474.6 46.4  26.04 Vo

ID    1.77 or 6.29 RG=1M RS=2.4k
11.52 11.52 RL=2.4k
VGS   1.77mA  2.4k   4.25V or  6.29mA  2.4k   15.1V
Rin
But VGS  15.1V beyond VP  8V  neglected Ro
 2I DSS  VGS  28  4.25 
 gm  1 


  1    0.94mS
VP  VP   8   8 

1
Ro  RS // 1 / gm   2.4k // k  2.4k // 1.06k  0.74k
0.94
Rin  RG  1M
vo g (R // RL ) 0.94(2.4k // 2.4k) 1.13
Av   m S    0.53
v in 1  gm RS // RL  1  0.94(2.4k // 2.4k) 2.13
 Summary of Design Equations
(in addition to dc design equations for EF configuration)
VDD VDD

R2

Circuits R1
RG
RS RS RL
RL

Input / output resistance Rin = RG Ro = RS//1/gm

I
Optimum gm  Opt. point gm  1.42 DSS
VP

gm (RS // RL )
Voltage gain Av   1  if 1  gm RS // RL 
1  gm RS // RL 
Design note:
SF – FET circuit has unity gain but it is required to design to produce a very
small output resistance
VDD

SF Self-bias FET Optimum bias

condition has VS = IDRS = -VGS is very
small so that the output (pp) will be
RG
very small. Such circuit can be only RS RL
used as a small –signal amplifier.

VDD

SF Voltage-divider bias FET Optimum

bias condition has VGS = VGG - IDRS and
therefore can be designed for large-
signal amplifier allowing to take RG
VS=VDD/2 RS RL
 Example

Draw JFET voltage-divider bias SF amplifier circuit and design the value of
required RG , RS = RL and VDD of a if the FET data is IGSS=1mA, IDSS=5mA and
VP=-3V, The required specification is VS=VDD/2 and Av = 0.7. Find Ro of your
amplifier

Opt . I D  5 mA / 2   2.5 mA  Opt . VGS  0.3  ( 3 )  0.9V

I 5 mA VDD
Opt . gm  1.42 DSS  1.42  2.367 mA / V 
VP 3
2.367 mA( RS // RL ) k 0.7
Av  0.7   RS // RL    1k
1  2.367  RS // RL  2.367  1.66
V
I D RS  DD  2.5 mA  2 k  5V  VDD  2  5  10V RG
RS
2 RL
VGG  VGS  I D RS  0.9  5  4.1V
0.1VP 0.3 V 12
RG    0.3 M  300 k R2  RG DD  300 k  878 k
I GSS 1 A VGG 4.1
RG 300 k
R1    455.7 k
VGG 4.1
1 1
VDD 12 Ro  RS // 1 / g m   2 k //( 1 / 2.37 ) k  348 
 Bootstrap Amplifier and design
Miller’s Theorem
I1 I2 I1 I2
Z

V1 V2 V1 ZM1 ZM2 V2

Rin
V V Z
Z M1  1  1
V V2 V V1 I 1 V1 V2
I1  1 and I 2  2
Z Z Z Z
   Input resis tan ce
V2 1  A
1 V V
1

V V Z Z
Z M2  2  2 
I 2 V2 V1 1 V1
V2
Z
  resis tan ce at output ter min al
1  1A
V

V
Where AV  2
V1
Miller’s Theorem applied to Bootstrap amplifier

I1 I2 I1 I2
Z
V1 V2 V1 ZM1 ZM2 V2

Rin VDD
VDD
RD
RD Vo
Vo Vin
Vin
Vo1
Vo1 RL
RL RS1
RG RS1 RM1 Vo2

Vo2 Rin
Rin RS2 RM2
RS2

Miller’s resistor RG RG
RG RS3  RM2 
Rin  RM1  1  1A
is connected 1  AV V
between Vin and Vo2
 Example: Find Rin of the folowing Bootstrap CS amplifier .
VDD
1. Find gm
Vp  8V, IDSS  8mA, RS  1k but VGS  IDRS1  1  ID RD
2 2 Vo3
 V    ID  8 Vin
 ID  IDSS 1  GS   81     8  ID 2
 VP   8  64
8ID  64  ID2  16ID  ID2  24ID  64  0 Vo2
RG
  24   576  256 24  17.89 300k 1k RS1 RL
ID    3.05 or 20.945 Vo1
11.52 2
 VGS   3.05  1k   3.05V or  20.9mA  1k   20.9V Rin 1.2k RS2
But VGS  20.9V is beyond VP  8V  neglected
 2IDSS  V   28  3.05 
gm  1  GS   1    1.24mS
VP  VP   8   8 
 
Vo3

2. Find Vo1/Vin=AV1 Vin gmVgs

v
Av1  o1 
gmVgs RS2 1.24mS(1.2k) 1.488
 0.399
Vgs RL

vin Vgs   gmVgs RS1  RS2  1  1.24mS(2.2k) 3.728

  RG
300k 1k RS1 RD
Vgs Vo1

3. Find Rin = RM1 Rin 1.2k RS2

RG 300k
Rin  RM1    499k (RG connected fromVin to Vo1 )
1  AV1 1  0.399
 Example
Draw JFET bootstrap amplifier and design the values of R s1 , Rs2 and RG of
the to have input impedance of 100M. FET has IGSS=10nA, IDSS=30mA, Vp=-
4V. Take optimum ID and voltage drop across RG is allowed to 10% of Vp.
I D  0.5 I DSS  0.5  30 mA  15 mA,VGS  0.3V p  0.3  4  1.2V , VDD

gm  1.42 ( I DSS / V p )  1.42  ( 30 / 4 )  10.65 mS

RD
0.4 0.4 Vo
Drop across RG  VRG  0.1V p  0.4V  RG    40 M Vin
I GSS 10  10  9
VRG  VGS  I D Rs 1  0.4  1.2  15 mA  Rs 1  RS 1  ( 1.6 / 15 ) k  106.6 
Vo1
RG 40 M RL
Rin  100 M  RM 1   ( RG connected fromVin to Vo 2 ) RG RS1
1  AV 2 1  AV 2
V Vo2
40 M
 Re quired AV 2  o 2  1   1  0.4  0.6 Rin
Vin 100 M RS2

V 
g mv gs Rs 2  g m Rs 2
But AV 2  o 2 
Vin     
v gs  g mv gs ( RS 1  Rs 2 ) 1  g m ( RS 1  Rs 2 )
Miller’s resistor RG
10.65 Rs 2
 is connected
1  10.65 ( RS 1  Rs 2 ) between Vin and Vo2
10.65 Rs 2
Therefore AV 2  0.6   0.6  6.39 ( 0.1066  Rs 2 )  10.65 Rs 2
1  10.65 ( RS 1  Rs 2 )
4.26Rs 2  0.6  0.68  1.28  Rs 2  0.305 k  305 
 CG Amplifier design
VDD VDD

RD RD
VO VO
R2

RL RL
C1 C1
Vin Vin
RG RS R1 RS
Rin Rin

JFET-self-bias CG amplifier JFET-v.divider-bias CG amplifier

VDD

RD
VO
R1

RL

C1 Vin

R2 RS
Rin

DMOS-v.divider-bias CG amplifier
 CG amplifier analysis: JFET-self-bias CG amplifier

VDD

RD
VO

Vo   g mv gs  RD // RL  but Vin  v gs RL

Vo  g mv gs  RD // RL  C1
 AV    g m RD // RL   Vin
Vin  v gs RG RS
Rin

Vin  v gs and I   g mv gs
G D
V  v  + +
Rin  RS //  in I   RS //  gs  g v  Gate
   m gs  capacitor vgs gmvgs RG RL
short - S
vo
 RS //  1 g  + I
 m RS vin Rin
- -
 CG amplifier analysis: JFET-v.divider-bias CG amplifier

VDD G D
RD
VO Gate + +
R2
capacitor vgs gmvgs RG RL
RL short - S
C1 vo
Vin + I
R1 RS RS vin Rin
Rin
- -
Vo  gmvgs  RD // RL  but Vin  vgs
Vo  gmvgs  RD // RL 
 AV    gm RD // RL 
Vin  vgs

Vin  vgs and I  gmvgs

 Vin    vgs  1 
Rin  RS //    RS //  g v   RS //  g 
 I    m gs   m
 Summary of Design Equations
(in addition to dc design equations for CG configuration)
VDD VDD

RD RD
VO VO
R2

RL RL
Circuits C1
Vin
C1
Vin
R1 RS R1 RS
Rin Rin

Input / output resistance Rin  RS //  1 g  Ro = RD

 m

Optimum gm I
 Opt. point gm  1.42 DSS
VP

Voltage gain AV  gm RD // RL 

 Example 1
Draw a JFET voltage-divider bias CG amplifier circuit and design the value
of required RG , RD = RL , RS , R1 , R2 of if the FET data is IGSS=1mA, IDSS=5mA
and VP=-3V,Take VDD = 40V. The required specification is Av = 10 and Rin =
600W. Find VD of your amplifier
Opt . I D  5 mA / 2   2.5 mA  Opt . VGS  0.3  ( 3 )  0.9V
5 mA
Opt . gm  1.42  2.367 mA / V  VDD
3
10 RD
AV  10  g m RD // RL   RD // RL   k  4.22 k R2
VO
2.367
 RD  RL  8.44 k RL
C1
VD  VDD  ID RD  40  2.5 mA  8.44 k  40  21.1V  18.9V Vin

422  600 R1 RS
Rin  600  RS // 1 / 2.367   RS   1.423k
600  422 Rin

VGG  VGS  I D RS  0.9  2.5 mA  1.423 k  2.66V

0.1VP 0.3
RG    0.3 M  300 k
I GSS 1 A
RG 300 k
R1    321 k
VGG 2.66 V 40
1 1 R2  RG DD  300 k  4.51 M
VDD 40 VGG 2.66
 Example 2
Draw a JFET self- bias CG amplifier circuit and design the value of required
RG , RD = RL , RS of if the FET data is IGSS=1mA, IDSS=5mA and VP=-3V,Take
VDD = 40V. The required specification is Av = 10 . Find VD and Rin of your
amplifier

Opt . I D  5 mA / 2   2.5 mA  Opt . VGS  0.3  ( 3 )  0.9V

5 mA VDD
Opt . gm  1.42  2.367 mA / V 
3 RD
VO
10
AV  10  g m RD // RL   RD // RL   k  4.22 k
2.367
RL
RD  RL  8.44 k C1
Vin
0.9 RG
VGS  0.9  I D RS  RS   360  RS
2.5 mA Rin
VD  VDD  I D RD  40  2.5 mA  8.44 k  18.9V
360  422
Rin  0.36k //1 / 2.367 k  Ro   194.3
360  422
 Summary of Design Equations
(dc design equations for all CS, CS with RS, SF, CG
V DD
configurations)
RD I Optimum IDQ Design equation
ID  DSS and VGS  0.3VP
2

+V 0.1VP RG Design equation

RG 
GS
-+ IGSS
RG RS ID
VGS  IDRS VGS Design equation for self-bias
-
V R
VGS  VGG  IDRS Where VGG  DD 1 VGS Design equation for Voltage
R1  R2
Divider bias
VDD V
R2  RG DD R2 Design equation
VGG
RD
R2 RG
R1  R1 Design equation
VG 1  VGG / VDD 
+V
-+
GS
R1 RS ID Vo (pp)  2  IDQ Rac Vo(pp) Design equation

-
 FET Summary
1. The Field Effect Transistor, or FET, is a voltage-controlled device.
2. FET has three terminals the source (S), drain (D) and gate (G).
3. FET have very high input impedance and has approximately 0 Amps of gate
current ( IG = 0A , therefore ID = IS ).
4. For E-MOSFET, the value of VGS that is just sufficient to produce a significant
channel for current ( ID ) to flow from drain region D to the source region S is
known as the Threshold Voltage, VT.
5. The transfer characteristic curve of E-MOSFET obeys the following equation.
6. ID = K (VGS - VT) 2 where: VGS > VT
7. There are three basic types of FET amplifiers: Common-Source Amplifier,
Common-Drain Amplifier, and Common-Gate Amplifier.
8. An E-MOSFET usually employ the voltage divider bias method, the d.c. analysis.
 FET Summary
9. 1) The gate voltage is given by the following expression:
VG = (R2 VDD) / (R1 + R2)
2) Applying KVL around the gate terminal loop (with R S), we have:
VG = VGS + RS ID
3) The bias line equation is as follows:
ID = (VG – VGS) / RS -- Bias line equation
4) Together with the E-MOSFET transfer characteristic equation
{ID = K (VGS–VT)2 } and the bias line equation, we can determine the
Q- point (the intersecting point) on the transfer characteristic co-ordinates
10. In analyzing ac signal, the small-signal drain current id of a MOSFET can be calculated from the
small-signal equivalent circuit of the transistor circuit.
11. The transconductance (gm) is the gradient at the Q-point on the transfer characteristic curve. It
is expressed by the following equation:
gm = id / vgs
12. From the small-signal ac equivalent circuit, we can derive the following values of the common-
source amplifier:
Input resistance, rin = RG = R1 // R2 ,
Output resistance, rout = rac = RD // RL,
Voltage gain, AV = vout / vin = –gm (RD // RL)
13. The gradient (or slope) of the ac load line is equal to rac = RD // RL.
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