Lecture 5

August 23, 2023

1
 Transistor –Biasing
Normal operation of transistor
𝐽 𝐸𝐵 ( 𝐸𝑚𝑖𝑡𝑡𝑒𝑟 − 𝐵𝑎𝑠𝑒 𝐽𝑢𝑛𝑐𝑡𝑖𝑜𝑛 𝑠h𝑜𝑢𝑙𝑑 𝑏𝑒 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑏𝑖𝑎𝑠)
𝐽 𝐶𝐵 ( 𝐶𝑜𝑙𝑙𝑒𝑐𝑡𝑜𝑟 − 𝐵𝑎𝑠𝑒 𝑗𝑢𝑛𝑐𝑡𝑖𝑜𝑛 𝑠h𝑜𝑢𝑙𝑑 𝑏𝑒𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠)

Mode of operation
CE CB CC
𝑅𝐿 𝑅𝐿

𝑉 𝐶𝐶

𝑅𝐿 𝑉 𝐸𝐸

𝑉 𝐵𝐵 𝑉 𝐶𝐸 𝑉 𝐵𝐵
𝑉 𝐶𝐶

2
 Transistor Characteristics

𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 𝑪𝒉𝒂𝒓𝒂𝒄𝒕𝒆𝒓𝒊𝒔𝒕𝒊𝒄𝒔

𝑰𝒏𝒑𝒖𝒕 𝑶𝒖𝒕𝒑𝒖𝒕
vs vs
Output voltage is parameter Input current is parameter
In CE configuration In CE configuration
(mA) vs (V) (mA) vs (V)
(V) parameter (mA) parameter 3
 Transistor characteristics PNP

𝐴2
+¿ −
𝑇
𝐴1 −
𝐵1 − +¿ −
𝑉2
𝑅2
𝐵2
𝑅1
𝑉1
+¿
+¿

A circuit arrangement to study transistor characteristics for CE configuration

4
 Transistor characteristics PNP
𝑰𝒏𝒑𝒖𝒕 𝒄𝒉𝒂𝒓𝒂𝒄𝒕𝒆𝒓𝒊𝒔𝒕𝒊𝒄𝒔 𝑶𝒖𝒕𝒑𝒖𝒕 𝒄𝒉𝒂𝒓𝒂𝒄𝒕𝒆𝒓𝒊𝒔𝒕𝒊𝒄𝒔
mA

4 − 80 A

V
3 −60

V
V
V

A
(mA)

(mA)
− 0.2 − 40
A
− 0.1 −20
0
0 0
− 0.2 4 − 0.6 − 0.2 4 − 0.6 4 − 0.6
(V) (V) 5
 Transistor characteristics PNP
Output characteristics:
mA
1) Active region (, )
− 80 A

A
2) Saturation region (, ) −60
A

(mA)
− 40
3) Cutoff region (, ) A
−20
0
0
− 0.2 4 − 0.6 4 − 0.6
(V)
6
Transistor as a switch PNP

Input

Output

7
 Transistor Biasing

Kirchhoff’s voltage law

𝐼𝐶
𝑅𝐿 𝑉 𝐶𝐶=− 𝐼 𝐶 𝑅 𝐿 −𝑉 𝐶
𝑅𝑔
+¿
𝐼𝐵 𝑉 𝐶𝐶 𝑉 𝐶
𝑉𝐶 𝑉 𝐶𝐶 𝐼 𝐶 =− −
𝑅𝐿 𝑅𝐿
+¿
𝑉 −
𝐵
− 𝐼𝐸
𝑉 𝐵𝐵

8
 Transistor Biasing-LOAD LINE
𝐼 𝐶 (𝑚𝐴)
𝑉 𝐶𝐶 𝑉 𝐶
𝐼𝐶 ( 𝑉
0 ,− 𝐶𝐶
𝑅𝐿 ) 𝐼 𝐶 =−
𝑅𝐿
−
𝑅𝐿

𝑅𝑔 𝑅𝐿
+¿
𝐼𝐵 𝐿𝑜 1
𝑉𝐶 𝑉 𝐶𝐶 𝑆𝑙𝑜𝑝𝑒 =−
𝑎𝑑 𝑅𝐿
+¿
𝑉 − 𝑙𝑖𝑛
𝑉 𝐵𝐵 𝐵
𝑒
− 𝐼𝐸
(−𝑉 𝐶𝐶 , 0)
𝑉 𝐶 (𝑉 )

𝑅 𝐿 =300 Ω , 𝑉 𝐶𝐶=15𝑉 9
 Transistor Biasing
𝑶𝒖𝒕𝒑𝒖𝒕 𝒄𝒉𝒂𝒓𝒂𝒄𝒕𝒆𝒓𝒊𝒔𝒕𝒊𝒄𝒔 :𝑸 − 𝒑𝒐𝒊𝒏𝒕𝒔
.5 𝑚𝐴

(mA)
𝐼 𝐵=− 0
( 0 ,−
𝑉 𝐶𝐶
𝑅𝐿 ) A

A=
− 40
𝑄1
A
A −30 𝑄2
𝑄3 A
𝐿𝑜
−20 𝑄4 𝑎𝑑
𝑙𝑖𝑛 A
Output waveform −10
𝑄6
𝑒
0
𝑄7 (−𝑉 𝐶 𝐶 ,0)
0
−3 −6 −9 −12 −15
(V) 10
 Transistor Biasing → Q point
The choice of Q-point is determined by
1) The availability of supply voltage
2) The load resistance of amplifiers
3) The amplitude of the signal to be amplified
4) The allowable distortion of the output signal

The operating point can change due to the instability of the collector current .
There are three sources for the instability of
1) The reverse saturation current which doubles for every rise of temperature.
2) The base-emitter voltage that falls at the rate of 2.5 for both Ge and Si transistor.
3) which rises with temperature. The value of variation of with temperature is small and the
transistor is assumed to be in the active region where is practically independent of the effect
of the change of is ignored here.

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 Transistor Biasing FIXED BIAS (FB)

Using the Kirchhoff law

𝐼𝐶 𝑅𝐿 𝑉 𝐶𝐶 − 𝑉 𝐵𝐸
𝐼 𝐵=
𝑅𝐵
𝑅𝐵
𝑉𝑜
𝐶1 𝐼𝐵 The collector current
𝑉 𝐶𝐶
Input
+¿
𝑉 𝐼 𝐶= 𝜷 𝐼 𝐵 +¿
𝐵𝐸
Signal
−
𝑉 𝐶𝐶 − 𝑉 𝐵𝐸
𝐼 𝐶= 𝜷 +¿
𝑅𝐵
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 Transistor Biasing Stability Factors
FIXED BIAS (FB)
Lower the stability factor, the better stability of Q-point
𝛿 𝐼𝑐
𝑺= = 𝜷 +1
𝛿 𝐼 𝐶𝑂

′ 𝛿 𝐼𝑐 𝜷
𝑺= =−
𝛿 𝑉 𝐵𝐸 𝑅𝐵

13
 Transistor Biasing C to B bias (CB)
Collector to Base Bias
Using the Kirchhoff law
𝐼 𝐶+ 𝐼 𝐵 V CE = I B RB +V BE
𝑅𝐵 𝑅𝐿 V CC =(I C + I ¿ ¿ B)R L +V C E ¿
𝑉𝑜
Using the above equations
V CC =( I C + I ¿ ¿ B) R L + I B R B +V BE ¿
𝐶1 𝐼𝐵 𝑉 𝐶𝐶
𝑉 𝐶𝐶 − 𝑉 𝐵𝐸 − 𝐼 𝐶 𝑅 𝐿
𝐼 𝐵=
+¿
𝑉 𝑅𝐵+ 𝑅𝐿
Input 𝐵𝐸
Signal − 𝐼 𝐶 = 𝛽 𝐼 𝐵 +¿
Substituting for and rearranging

𝐼𝐶
( 1+
𝛽 𝑅𝐿
𝑅𝐵+ 𝑅𝐿
=𝛽
)
(𝑉 𝐶𝐶 − 𝑉 𝐵𝐸 )
+¿
𝑅 𝐵 + 𝑅 𝐿 ❑ 14
 Transistor Biasing Stability Factors
Collector to Base Bias
Lower the stability factor, the better stability of Q-point
𝛿 𝐼𝑐 𝜷 +1
𝑺= =
𝛿 𝐼 𝐶𝑂 1+ 𝜷 𝑅 𝐿 /( 𝑅 𝐿 + 𝑅 𝐵 )

′ 𝛿 𝐼𝑐 𝜷
𝑺= =−
𝛿 𝑉 𝐵𝐸 𝑅𝐵 + 𝑅 𝐿 ( 𝜷 +1)

′′ 𝛿 𝐼 𝑐 𝑉 𝐶𝐶 −𝑉 𝐵𝐸 − 𝐼 𝐶 𝑅 𝐿 +( 𝑅 𝐵 + 𝑅 𝐿 ) 𝐼 𝐶𝑂
𝑺 = =
𝛿𝜷 𝑅 𝐵 + 𝑅 𝐿 ( 𝜷+1)

𝛿 𝐼 𝑐 𝑉 𝐶𝐶 − 𝐼 𝐶 𝑅 𝐿 +( 𝑅 𝐵 + 𝑅 𝐿 ) 𝐼 𝐶𝑂
<< ′′
𝑺 =
𝛿𝜷
=
𝑅 𝐵 + 𝑅 𝐿 ( 𝜷 +1)
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 Self-Bias or Emitter Bias
Emitter Bias
Thevenin source

𝐼𝐶 𝑅𝐿 𝑅2 𝑉 𝐶𝐶
𝐶2 𝑉 𝑇=
𝑅1 𝑅 1+ 𝑅2
𝑉𝑜 𝑉 𝐶𝐶
𝐶1 𝐼𝐵
Thevenin resistance
+¿
𝑉
𝐵𝐸
− 𝑅 1 𝑅2
Input 𝑅𝑇 =
Signal 𝑅2
𝐶𝑒 𝑅 1+ 𝑅2
𝑅𝑒

16
 Self-Bias or Emitter Bias
Emitter Bias
Thevenin source

𝐼𝐶 𝑅𝐿 𝑅2 𝑉 𝐶𝐶
𝑉 𝑇=
𝑅 1+ 𝑅2
𝑅𝑇 +¿ 𝑉 𝐶𝐶
𝑉 𝐶𝐸
Thevenin resistance
𝐼𝐵 +¿ −
𝑉 𝐵𝐸 𝑅 1 𝑅2
− 𝑅𝑇 =
𝑉𝑇
(𝐼 ¿ ¿𝑐+𝐼 𝐵 )¿
𝑅 1+ 𝑅2
𝑅𝑒

17
 Self-Bias or Emitter Bias
Emitter Bias
Using the Kirchhoff law around base
I B R T +V B E +( I B + I C ) R 𝑒=V 𝑇
𝐼𝐶 𝑅𝐿
𝑽 𝑻 −𝑽 𝑩𝑬 − 𝑰 𝑪 𝑹𝒆
𝑰 𝑩=
𝑹𝑻 + 𝑹 𝒆
𝑅𝑇 +¿ 𝑉 𝐶𝐶
𝑉 𝐶𝐸 Using the Kirchhoff law around Collector
𝐼𝐵 +¿ − R e ( I 𝑐 + I 𝐵 )+ I 𝐶 R 𝐿 +V CE =V 𝐶𝐶
𝑉 𝐵𝐸
− >> ,
𝑉𝑇
𝑅𝑒 (𝐼 ¿ ¿𝑐+𝐼 𝐵 )¿

𝐕 𝐂𝐄=− 𝐈 𝑪 ( 𝑹 𝑳+ 𝑹𝒆 )+ 𝐕 𝑪𝑪
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 Self-Bias or Emitter Bias- Q point
Emitter Bias
LOADLINE
2V 𝐕 𝐂𝐄=− 𝐈 𝑪 ( 𝑹 𝑳+ 𝑹𝒆 )+ 𝐕 𝑪𝑪
8 Load line slope:
𝐿𝑜
𝑎𝑑 A BIAS CURVE
6 𝑙𝑖𝑛 I B R T +V B E +( I B + I C ) R 𝑒=V 𝑇
𝑒 𝐵𝑖𝑎𝑠 𝑐𝑢𝑟𝑣𝑒
(mA)

4 A
A relation between and to be achieved. For
each vale of marked on the collector
𝑄
1 A curves, calculated from the relationship.
The interaction of the dc loadline and the
0 𝑚𝐴 bias curve gives the quiescent point Q.
0
0 2 5 6 8
(V) 19
 Self-Bias or Emitter Bias- Stability factors
Emitter Bias
The collector current can be represented as 𝐼 𝐶 = 𝛽 𝐼 𝐵 +¿

𝑉 𝑇 −𝑉 𝐵𝐸 − 𝐼 𝐶 𝑅𝑒
The base current can be represented as 𝐼 𝐵=
𝑅𝑇 + 𝑅𝑒
Using above 2 eqn: 𝐼𝐶
( 1+
𝛽 𝑅𝑒
𝑅𝑇 + 𝑅𝑒 )=
𝛽𝑉 𝑇
𝑅𝑇 + 𝑅 𝑒
−
𝛽 𝑉 𝐵𝐸
𝑅𝑇 + 𝑅𝑒
+¿

𝛿 𝐼𝑐 𝜷+1 𝟏+ 𝑅 𝑇 / 𝑅 𝑒
𝑺= = =( 𝜷+1) ¿
𝛿 𝐼 𝐶𝑂 1+ 𝜷 𝑅 𝑒 /( 𝑅 𝑇 + 𝑅𝑒 ) 1+ 𝜷 + 𝑅𝑇 / 𝑅𝑒 ¿

′ 𝛿 𝐼𝑐 𝜷
𝑺= =−
𝛿 𝑉 𝐵𝐸 𝑅𝑇 + 𝑅𝑒 ( 𝜷 +1)

′′ 𝛿 𝐼𝑐 1
𝑺 = = ¿
𝛿 𝜷 𝜷 ( 𝜷 +1 ) 20
 Comparison of biasing

Which is the best biasing condition?

Fixed bias, Collector to Base bias and Emitter bias
Advantages?

Disadvantages?

21
 Bias compensation with diode
+𝑉 𝐶𝐶

𝐼𝐶 𝑅𝐿 Working mechanism ?
𝐶2
𝑅𝐵 𝐼
𝑉𝑜 Advantages?
𝐼𝐵
Disadvantages?
Input
Signal 𝐼𝐷

22
 Bias compensation using a Thermistor
+𝑉 𝐶𝐶

𝐼𝐶 𝑅𝐿
𝐶2
𝑅1
𝑉𝑜
𝐼𝐵 Working mechanism ?
Input
+¿
𝑉 Advantages?
𝐵𝐸
Signal −
𝑅2
𝑅𝑇
𝑅𝑒
𝐶𝑒 Disadvantages?

23
 Concept Question-4
1. Calculate the values of three currents in the circuit shown in Figure below.(Take
base-emitter voltage VBE = 0.)

24
 Concept Questions - 5
2. For a given CE amplifier, operating point is VCE = 8V and IC = 2 mA. You are
supplied with a fixed 15V d.c. supply and a silicon transistor with β = 100. Take base-
emitter voltage VBE = 0.6V. Calculate the value of load resistances that would be
employed.

25
 Concept Questions - 6
3. For the given base bias circuit, determine VCE and IC.(Take base-emitter voltage
VBE = 0.7V.)

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