Yield and reject rate

Defect level is same as reject rate

Number of single and multiple faults
Number of collapsed faults
Collpased faults in the below circuit
Scan rules
Tristate buses
Tristate buses
Bidirectional_ports
Bidirectional_ports
Clock gating-DFT
Derived clocks
Derived clocks
Combinational Feedback loops
combinational feedback loops
Asynchronous set/reset signals
Asynchronous set/reset contd…
Lock up latches
Lock up latch not required
 Small delay defects
• Small Delay Defect actually tries to capture faults which are very small in
magnitude. If you understand transition fault then you will agree that a fault will be
detected if and only if it bigger then the slack available on the path on which it is
detected.

For example lets take a fault of magnitude 2ps also assume that this fault is
detected on a path with available slack of 5ps. So, even if this fault does come on a
fabricated chip the patterns will pass. But at the same time this 2ps fault comes on
a critical path with available slack of 1ps then the chip is going to fail but the
patterns will pass.

Now the current ATPG tools in transition tries to detect the fault on the shortest
path that is with maximum slack , but if we some how target the same fault on the
longest path i.e with least slack then the chances that even the small fault will get
detected when on ATE.